Introduction –

The PCB was designed with the primary objective to test the FAME-ASIC. The board is made such that it sits over the SAKURA-G board, and is pin compatible with the same, but care should be taken to properly orient the board such that the controller FPGA header on the FAME-PCB is aligned with the one on SAKURA-G board.

The diagram below gives us an upper-level view of the PCB. It basically lists down all the necessary blocks required to test the functionality of the FAME-ASIC.

--Diagram--

NOTE:- There are two versions of this PCB manufactured, with the second overcoming some of the problems that the first one had. Here is the brief description of the basic schematics of this board, the differences and the care to be taken before using these boards is mentioned in the version(revision) specific pages in this Wiki.

The important modules/blocks, as mentioned here are –

1. Power Supply
2. UART to USB
3. FAME-ASIC
4. Connection Headers
5. Voltage Translators

Description

1. POWER SUPPLY
   The FAME-ASIC requires two voltage levels for its operation – 1.8 V (Core Voltage) and 3.3V (I/O voltage). The power supply takes care that these voltages are effectively generated and decoupled. It has two options to draw power (3.3V). SAKURA-G board and External supply (DC Jack). This voltage is stepped down to 1.8V using a LDO regulator for the core voltage.
   It has a power measurement setup which includes a 1ohm resistor in series with the power supply, and voltage across it can be used to measure power consumption.
   It also includes an on-board voltage glitcher which uses a MOSFET to short the input voltage to ground for a brief amount of time. This glitch signal can be controlled using the controller FPGA on the SAKURA-G board.

2. USB to UART
   This module sits between the ASIC and the computer used for communication. It converts the UART protocol to USB and vice-versa to enable data transfer. This is crucial for debugging and observing the performance of the ASIC. It involved 3 different interfaces – debug-1, debug-2 and user UART.

3. FAME - ASIC
   This defines the immediate connections of the ASIC. 4 LEDs are connected to the GPIO pins to show their output values.

4. CONNECTION HEADERS
   These include most of the input/output interfaces on the PCB. Importantly, it involves the input clock for voltage glitching (SMA connector), controller FPGA header, and some test-points.

5. VOLTAGE TRANSLATORS
   The voltage translators are used to convert the voltage levels from 2.5V (SAKURA I/O operating voltage) to 3.3V (ASIC I/O operating voltage).

Notes on features

1. POWER MEASUREMENT
   The power measurement circuit provides two SMA connectors which can be used to probe voltages. A 1 Ohm resistor is placed in series between these two SMA connectors, which provides a small voltage drop proportional to the current flowing through the resistor. This difference in the voltages can be used to measure the power consumption of the processor core.

2. ON-BOARD VOLTAGE GLITCHER
   The on board voltage glitcher uses a MOSFET to short the 1V8 (core voltage) to ground. This MOSFET can be triggered by a signal from the FPGA. There is a selector to select the connection of the gate of the MOSFET. This should be towards GND by default. Only before insertion of glitches, should this be shifted to the FPGA GLITCH side.

3. EXTERNAL VOLTAGE GLITCHER
   In case an external voltage glitcher has to be connected, it has to be connected across the J5 connector (with +ve terminal towards the side where J5 is written on the board). In case an external voltage glitcher is connected, the POWER_JUMPER should be disconnected. This isolates the LT3083 from the circuit.