Increasing a page by a factor of X decreases the size of a page table by a factor of 4!

Remember that Semgments use base registers and limits, base used to show where in physical addresss the segment is, and limits to show how big that segment is.

We can segment the process into 3 parts, code, stack, and heap.

Each segment has base register and limits.

The limit represent the max number of pages now though. And the base register represents where a page table is for that particular segment.

SO a VA looks like:

			[Seg | VPN | Offest]

Hybrid approach still has the issue that seg brings, it's not flexible and forces us to pattern the address space in a specific way, leading to wasting memory with a page table if a heap segment is seldom used.

Also, it leads to extern frags, page tables can be a varied number amount now.

Not just having a PT Base Reg now, we also have a PD Base Reg.

Think of this as an matrix. There's now a page directory table. Each page directory table entry holds the location of a page table. Thus, it creates now a matrix of page table entries, rather than just an array of pages table entries as seen from the 1 level paging in chapter 18.

Another good analogy would be an array of string pointers. The array that holds the string pointers is the page directory table. Each string can be thought of as a page table. And each character in that string is a page table entry.

A specific element in this matrix represents a page table entry, thus representing a frame. In contrast to 1 level paging, you need know a row and a column index to access this matrix's element, rather than just needing an array index (a page number).

So a page directory index thus would specify the row of this matrix, and a page table index specifies the column, thus leading you straight to the page table entry. The virtual address needs to be changed from chapter 18:

			VA: [Page Directory Index | Page Table Index | Offset for specific page/frame ]

PDE entry has:

• valid bit
  • valid bit is set if the page table that the PDE entry refers to has at least 1 page that is present.
• page frame number
  • tells us where a page table is

PTE entry still has:

• valid bit
• protection bit
• Page Frame Nubmer
  • Tells us where the location of the frame in which the page is stored in.

So a physical address memory space is determined from the PFN. We look into the PTE, and see how many bits is used to represent a page frame number, let's call the number n. So we know there are thus 2^n total frames. Thus, physcal adress space = 2^n *sizeof(frame). Note, sizeof(frame) == sizeof(page).

So a virtual address memory space is found from looking at the virtual address. The VA tells us the bits needed for the page table index, let's call this n. So a page table thus has 2^n entries. Thus, 2^n entries times sizeof(page) will tell us how big the virtual address space is, for just one page directory entry. The VA tells us the bits needed for the frame directory index, let's call this n. So a page directory thus has 2^n entries. Thus, there are 2^n page tables. Thus, total virtual address memory space is (2^n) * (2^n) * sizeof(page).

You can determine if you need more than 2 levels easily. You just have to keep adding a new level until your Page Directory Table fits in one page size.

e.g. if the Page Directory Index bits is 14 bits but a page can only hold 512/4 = 128 entries, you can say well let's have two page dirs, each using 7. So now you have 2^7 = 128 entries for each page directory. 512 represtns a page size in bytes. 4 represents size of Page Dir entry.