set WORK_DIR /hdd2/home/vamsy/FEB_2022/level4_projects/Final_lab set_context dft -rtl -design_id cpu_top_edt

Set the location of the TSDB. Default is the current working directory.

set_tsdb_output_directory $WORK_DIR/tsdb_outdir

No need to read in the design using read_verilog. It can be read directly from the TSDB.

read_design cpu_top -design_id cpu_top_mbist -verbose

Reading Mem Libs and Pad libs

read_cell_library ../../DATA/libs/tphn40lpgv2od3_sl.mdt read_cell_library ../../DATA/libs/tcbn40lpbwp.mdt dofile ../../DATA/libs/DATA/memory_atpg.libs

Design sources/ Include Directories ################;

set_design_sources -format tcd_memory -Y ./ -extension tcd_memory

Declare Design top level module name

set_current_design cpu_top

add_black_boxes -auto

Add DFT Signals

DFT Signal used for logic test

add_dft_signals ltest_en

add_dft_signals scan_en edt_update test_clock -source_node { rx_core_u0/u_pin_mux/scan_enable rx_core_u0/u_pin_mux/edt_update EXT_CLK }

report_dft_signals

Create shift_capture_clock and edt_clock as gated versions of test_clock

add_dft_signals shift_capture_clock edt_clock -create_from_other_signals

DFT Signal used by top-level EDT

add_dft_signals edt_mode

DFT Signal used for BoundaryScan to be used with logic test without contacting inputs

add_dft_signals int_ltest_en output_pad_disable

DFT Signal used for Scan Tested Instruments like memorybist/boundary scan

add_dft_signals tck_occ_en

DFT Signal used to bypass memories

add_dft_signals memory_bypass_en

report_dft_signals

add_nonscan_instance rf_0* add_nonscan_instance /rx_core_u0/clk_gen_inst* add_nonscan_instance /rx_core_u0/reset_gen_inst* add_nonscan_instance /cpu_top_cpu_top_mbist_tessent_sib_sti_inst*

Specify pre-DFT DRC rules

set_dft_specification_requirements -logic_test on

check_design_rules

dict set::auxiliary_data_dict <auxiliary input/output=>pin/select-line>

dict set ::auxiliary_data_dict SYS_MODE[1] auxiliary_input_pin rx_core_u0/u_pin_mux/scan_enable dict set ::auxiliary_data_dict SYS_MODE[1] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[5] auxiliary_input_pin rx_core_u0/u_pin_mux/edt_update dict set ::auxiliary_data_dict GPIO[5] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[15] auxiliary_input_pin rx_core_u0/u_pin_mux/scan_in[0] dict set ::auxiliary_data_dict GPIO[15] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[14] auxiliary_input_pin rx_core_u0/u_pin_mux/scan_in[1] dict set ::auxiliary_data_dict GPIO[14] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[13] auxiliary_output_pin rx_core_u0/u_pin_mux/scan_out[0] dict set ::auxiliary_data_dict GPIO[13] auxiliary_output_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[12] auxiliary_output_pin rx_core_u0/u_pin_mux/scan_out[1] dict set ::auxiliary_data_dict GPIO[12] auxiliary_output_enable_pin digital_pads_u0/pc_scan_sel

report_dft_control_points

Create and report a DFT Specification

Empty DFT specification for OCC and EDT are created here and populated later in this dofile

set spec [create_dft_specification -sri_sib_list {occ edt} ] report_config_data $spec

read_config_data -in $spec -from_string { OCC { ijtag_host_interface : Sib(occ); } }

Below is a generic way to populate the OCC. The clock list is design-specific and needs to be updated for the design

The scan_enable and shift_capture_clock signals are automatically connected to OCC instances

Modify the below list for your specific design requirements

set id_clk_list [list
clk1 /rx_core_u0/clk_pll
] foreach {id clk} $id_clk_list { set occ [add_config_element OCC/Controller($id) -in $spec] set_config_value clock_intercept_node -in $occ $clk } report_config_data $spec

The edt_clock and edt_update signals are automatically connected to EDT instances

The EDT controller is built with Bypass

Modify the below specification for your specific design requirements

The propery connect_bscan_segments_to_lsb_chains defaults to auto and connects the divided boundary scan segments from the previous pass to EDT

read_config_data -in $spec -from_string { EDT { ijtag_host_interface : Sib(edt); Controller (c1) { longest_chain_range : 470, 475; scan_chain_count : 107; input_channel_count : 2; output_channel_count : 2; Connections +{ EdtChannelsIn(1) { } EdtChannelsIn(2) { } EdtChannelsOut(1) { } EdtChannelsOut(2) { } } } } }

}

The EDT Channel In/Out pins which are equipped with auxiliary ports from the previous dict declaration need to be specified

set_config_value port_pin_name -in $spec/EDT/Controller(c1)/Connections/EdtChannelsIn(1) [get_single_name [get_auxiliary_pins GPIO[15] -direction input]] set_config_value port_pin_name -in $spec/EDT/Controller(c1)/Connections/EdtChannelsIn(2) [get_single_name [get_auxiliary_pins GPIO[14] -direction input]] set_config_value port_pin_name -in $spec/EDT/Controller(c1)/Connections/EdtChannelsOut(1) [get_single_name [get_auxiliary_pins GPIO[13] -direction output]] set_config_value port_pin_name -in $spec/EDT/Controller(c1)/Connections/EdtChannelsOut(2) [get_single_name [get_auxiliary_pins GPIO[12] -direction output]]

report_config_data $spec

Generate and insert the hardware

process_dft_specification

Extract IJAG network and create ICL file for the design

extract_icl

Creates a Synthesis script of ALL the RTL (orignial and newly-created) to be used in DC Shell in next Step

write_design_import_script -use_relative_path_to . for_dc_synthesis_edt_occ.tcl -replace

Generate patterns to verify the inserted DFT logic

set spec1 [ create_pattern_specification -replace]

process_pattern_specification

Point to the libraries and run the simulation

set_simulation_library_sources -v ../../DATA/libs/tcbn40lpbwp.v -v ../../DATA/libs/tphn40lpgv2od3_sl.v

report_simulation_library_source

run_testbench_simulations -generate_scripts_only