set WORK_DIR ~/FEB_2022/level4_projects/Final_lab set DESIGN_DIR ~/FEB_2022/level4_projects/Final_lab/DATA/files/list

Declaring context to perform mbist on RTL

set_context dft -rtl -design_id cpu_top_mbist

General setup of directories

system mkdir reports_dft system rm -rf simulation_outdir

Mention the output directoy name and path to store the output files

set_tsdb_output_directory $WORK_DIR/tsdb_outdir

Reading Mem Libs and Pad libs

dofile ../DATA/libs/DATA/std_cells_libs.dofile dofile ../DATA/libs/DATA/memory_libs.dofile

DFT cell selection

read_cell_library ../DATA/libs/DATA/dft_cell_selection

Design sources/ Include Directories ################;

set_design_sources -format tcd_memory -Y ./ -extension tcd_memory set_design_include_directories $DESIGN_DIR/design/defs/

Reading Design RTL Files

dofile inputs/rtl_files.dofile

Declare Design top level module name

set_current_design cpu_top

add_black_boxes -auto

report_design_sources

report_black_boxes

set_design_level chip

Constraints to control

## Scan mode for design 

add_pin_constraints SCAN_SEL C1 ; # dedicated pin for DFT - that can be also be used for pin_mux control #add_pin_constraints SYS_MODE[0] C1

add_clocks 0 F_CLK -period 20 ns -pulse_always add_clocks PLL/CLKOUT -REFERENCE F_CLK -FREQ_Multiplier 8 -label pll_out

Scan reset

add_pin_constraints RESET_N C1

JTAG insertion

set_attribute_value DEBUG_MODE -name function -value tck set_attribute_value GPIO[7] -name function -value tdi set_attribute_value SYS_MODE[2] -name function -value tms set_attribute_value GPIO[10] -name function -value trst set_attribute_value GPIO[6] -name function -value tdo

## Enabling the memory bist 	

set_dft_specification_requirements -memory_test on

check_design_rules

set_config_value /DefaultsSpecification(user)/DftSpecification/use_rtl_cells off set_config_value /DefaultsSpecification(user)/DftSpecification/use_rtl_synchronizer_cell on

set spec [create_dft_specification]

read_config_data -in_wrapper $spec/IjtagNetwork -from_string { HostScanInterface(tap_internal) { Interface { tck : /rx_core_u0/u_pin_mux/jtag_clk; trst : /rx_core_u0/u_pin_mux/jtag_trstn; tms : /rx_core_u0/u_pin_mux/jtag_tms; tdi : /rx_core_u0/u_pin_mux/jtag_tdi; tdo : /rx_core_u0/u_pin_mux/jtag_tdo; tdo_en : /rx_core_u0/u_pin_mux/tdo_oen; tdo_en_polarity : active_low; } } }

move_config_element ${spec}/IjtagNetwork/HostScanInterface(tap)/Tap(main) -in_wrapper ${spec}/IjtagNetwork/HostScanInterface(tap_internal)

report_config_data $spec > reports_dft/default_spec

dict set -> this is a tcl command ; below section will describe the connectivity of existing pin_mux logic / structure to the corresponding top level PADS/ ports:

dict set ::auxiliary_data_dict SYS_MODE[1] auxiliary_input_pin rx_core_u0/u_pin_mux/scan_enable dict set ::auxiliary_data_dict SYS_MODE[1] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[5] auxiliary_input_pin rx_core_u0/u_pin_mux/edt_update dict set ::auxiliary_data_dict GPIO[5] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[15] auxiliary_input_pin rx_core_u0/u_pin_mux/scan_in[0] dict set ::auxiliary_data_dict GPIO[15] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[14] auxiliary_input_pin rx_core_u0/u_pin_mux/scan_in[1] dict set ::auxiliary_data_dict GPIO[14] auxiliary_input_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[13] auxiliary_output_pin rx_core_u0/u_pin_mux/scan_out[0] dict set ::auxiliary_data_dict GPIO[13] auxiliary_output_enable_pin digital_pads_u0/pc_scan_sel

dict set ::auxiliary_data_dict GPIO[12] auxiliary_output_pin rx_core_u0/u_pin_mux/scan_out[1] dict set ::auxiliary_data_dict GPIO[12] auxiliary_output_enable_pin digital_pads_u0/pc_scan_sel

process_dft_specification report_config_data $spec

extract_icl

set spec1 [create_patterns_specification signoff -replace ] report_config_data $spec1 report_config_data $spec1 > reports_dft/patterns_spec_signoff process_patterns_specification signoff

Running simualtions for generated patterns using tshell (internally invokes simulator)

set_simulation_library_sources -v ../DATA/libs/tcbn40lpbwp.v -v ../DATA/libs/tphn40lpgv2od3_sl.v

report_simulation_library_source

run_testbench_simulations -generate_scripts_only