Yosys ghdl rules algorithm details - VHDLTool/sonar-VHDLRC GitHub Wiki

CNE_02000 rule

  • Identify fsms with fsm_detect command and dump the results in a file.
  • Parse dump file to get the names of the fsms that yosys ignored.
  • For each ignored fsm, set attribute "fsm_encoding" to "auto". Thus, they will be taken into account during the following steps.
  • Extract and export fsms. Kiss2 files will be generated.
  • By parsing the name of each kiss2 file, get the name of the corresponding fsm and the path of its source file.
  • If the name of a fsm doesn't comply with the convention (defined by a regex), parse the source file to get the line where the signal encoding the fsm is declared, and raise an issue.

STD_03900 rule

  • Use the same algorithm as CNE_02000 rule to generate kiss2 files, and identify fsms and their source files.
  • Parse each file containing a fsm to identify the line where the signal encoding the fsm is declared.
  • Parse that line to get the type of the signal.
  • If the name of the type starts with "std_" or "ieee_", then an issue is raised.

STD_05200 rule

  • Get the list of outputs with "yosys> select o:* -module topmodule", "topmodule" being a parameter of the vhdlrc plugin. Dump results in a file.
  • Parse dump file to get the names of all output signals in the analyzed project.
  • Get the stats of each output and dump them.
  • Parse each stat file to identify the number of cells is null. If not, raise an issue.
  • To raise an issue precisely where the top entity is declared, the cf file (ie work-obj93.cf) generated with ghdl -a is parsed.
    Warning: yosys is case sensitive (and seems to be in lowercase) therefore the sonarqube parameter sonar.vhdlrc.topEntities should be in lowercase, otherwise yosys will not find the toplevel entity