Xilinx Tri mode Ethernet Mac Example Design - Terry4055/FPGA_HW GitHub Wiki

  1. ๊ตฌ์„ฑ
  • Data Generator <--Axi-stream--> FIFO <--Axi-stream--> Tri-mode Ethernet MAC IP <--RGMII--> Ethernet Trasceiver <--MDI 1000 Base-T--> RJ45 Connector
  1. ์ค‘์š” ๋‚ด์šฉ
  • RGMII(Reduced Gigabit Media Independent Interface) : GMII์— ๋น„ํ•ด Pin Count๊ฐ€ 50%๋กœ ์ค„์–ด๋“  DDR Flip Flop ๋ฐฉ์‹ ์ธํ„ฐํŽ˜์ด์Šค
  • Tri-mode Ethernet MAP IP
    • 10/100/1000 Mb/s Ethernet MAC, 10/1000Mb/s Ethernet MAC, 1Gb/s Ethernet MAC, 2.5Gb/s Ethernet MAC ์ง€์›
    • ๋ฐ˜์ด์ค‘, ์ „์ด์ค‘ ๋™์ž‘ ์ง€์›
    • 2๊ฐœ Main Physical Standards
      • BASE-T : twisted pair cabling system์„ ์‚ฌ์šฉํ•œ copper standard(SGMII, RGMII, MII, GMII with 10/100/1000bps)
      • BASE-X : short & long ํŒŒ์žฅ ๋ ˆ์ด์ €๋ฅผ ์‚ฌ์šฉํ•œ Fiber optical physical standard(PCS/PMA or SGMII with 1G/2.5Gbps)
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