Clock Controller - TechTechTechnologies/Prometheus GitHub Wiki

The clock controller is required to provide tuned clocks for the three LFSRs. What sorts of tuning are we interested in?

Octave Tuning

Where the LFSRs are tuned to three consecutive octaves

Unison Tuning

Where the LFSRs are tuned to the same note

Arbitrary Tuning

Where the LFSRs are tuned to three arbitrary notes

Basically this means that three different divider ratio registers need to be set.

In addition, we want to support some detuning modes. These might be achieved with three more detuning registers, which should implement signed offsets.

In order to divide a 50MHz clock to, say, 1kHz, we need a divider value for 50,000, which is larger than 15 bits, so we'll use 16-bit counters etc.

So the clock controller will have 3 1-bit outputs, 1 clock input, 1 set input, 1 reset input, a 3-bit register select line, and an 16-bit data line. There will then be three counters, three pairs of registers added together, and 3 comparators.

On a posedge of the clock, if reset, then set counters to 0. Else if set, then switch on the register select, latch the data line into the appropriate register, and set all counters to 0. Else, increment counters

Set three signal lines to counter == register+register. On each of those lines do on posedge, reset counter, invert output bit.