Synthesis & PnR - StanfordVLSI/dragonphy2 GitHub Wiki

Here's how to run synthesis and PnR on the Stanford infrastructure:

  1. Make sure that pip/python refer to a Python 3.7+ install, and check that you have cloned the DragonPHY repo and pip installed it along with Genesis2 (see wiki page on running tests for more information).
  2. Install mflowgen somewhere convenient:
> git clone https://github.com/cornell-brg/mflowgen.git
> export MFLOWGEN_HOME=`realpath mflowgen`
> cd mflowgen
> pip install -e .
> cd ..
  1. If you are targeting TSMC16 (will need to be on a machine with TSMC permissions to clone the repo shown)
> export DRAGONPHY_PROCESS=TSMC16
> cd $MFLOWGEN_HOME
> mkdir -p adks
> cd adks
> git clone http://gitlab.r7arm-aha.localdomain/alexcarsello/tsmc16-adk.git tsmc16
  1. If you are targeting FREEPDK45:
> export DRAGONPHY_PROCESS=FREEPDK45
  1. Set up the CAD environment (assumes that you're using bash; steps copied from .buildkite/pipeline.yml):
> module load base xcelium lc pts syn/latest genus innovus/19.10.000 icadv/12.30.712 calibre/2019.1
> export BUILD_VIEW=asic
  1. cd to the DragonPHY top-level directory and build the chip design (things like the JTAG register map...). If you already ran this before, the safest thing (to make sure that you're really re-running from scratch), is to remove the build directory, if it already exists.
> rm -rf build  # make sure that there isn't anything that you want to keep in there!
> python make.py --view asic
  1. Make a directory for running mflowgen and cd into it:
> cd build
> mkdir -p mflowgen
> cd mflowgen
  1. Set up mflowgen targets
> mflowgen run --design ../../designs/dragonphy_top/
  1. Run synthesis:
> make synopsys-dc-synthesis
  1. Check out the results:
  • Summary is in *-synopsys-dc-synthesis/reports/*.mapped.qor.rpt. Make sure that there are no setup or hold time violations. Also check that there are no transition time violations. There may be small violations of max capacitance or max fanout.
  • Review the violations of constraints: *-synopsys-dc-synthesis/reports/*.mapped.constraints.violators.rpt. For the max capacitance and fanout violations, make sure that these violations are small. If there are any setup or hold time violations, they will be explained in detail here.