"Design principles for packet parsers" G. Gibb, G. Varghese, M. Horowitz, and N. McKeown. ANCS '13, Oct. 2013.
“An area-efficient minimum-time FFT schedule using single-ported memory,” Stephen Richardson, Ofer Shacham, Dejan Markovic and Mark Horowitz. (To appear in) Proc. 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2013.
“Glen Thesis Name Place Holder,” Glen Gibb. Stanford 2013.
“Specifying and Validating Memory Protocols for Chip Generators” Megan Wachs. Stanford 2013. (pdfslides)
“FPU Generator for Design Space Exploration,” Sameh Galal, Ofer Shacham, John S. Brunhaver II, Jing Pu, Artem Vassiliev, Mark Horowitz. Proc. 21st IEEE International Symposium on Computer Arithmetic (ARITH21), 2013.
“Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation,” Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry Pileggi, Franz Franchetti, To appear in: The Journal of Signal Processing Systems
“Avoiding Game Over: Bringing Design to the Next Level,” Ofer Shacham, Megan Wachs, Andrew Danowitz, Sameh Galal, John Brunhaver, Wajahat Qadeer, Sabarish Sankaranarayanan, Artem Vassiliev, Stephen Richardson, Mark Horowitz. Proc. Design Automation Conference (DAC), 2012.
“Design Automation Framework for Application-Specific Logic-in-Memory Blocks,” Qiuling Zhu, Kaushik Vaidyanathan, Ofer Shacham, Mark Horowitz, Larry Pileggi and Franz Franchetti. Proc. Application-specific Systems, Architectures and Processors (ASAP) 2012.
"Polar Format Synthetic Aperture Radar In Energy Efficient Application-Specific Logic-In-Memory," Qiuling Zhu, Christian R. Berger, Eric L. Turnerz, Larry Pileggi, Franz Franchetti, Proc. International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2012.
"Application-Specific Logic-in-Memory for Polar Format Synthetic Aperture Radar," Qiuling Zhu, Eric L. Turner, Christian R. Berger, Larry Pileggi, Franz Franchetti. Proc. High Performance Embedded Computing (HPEC), 2011.(Paper pdf)
"Creating Chip Generators for Efficient Computing at Low NRE Design Costs," O. Shacham. High Performance Embedded Computing (HPEC) 2011. Invited talk. (Slides in pdf format)
"Chip multiprocessor generator: automatic generation of custom and heterogeneous compute platforms," O. Shacham. PhD Thesis, Stanford University 2011 (Stanford Digital Repository)
"Generating/Programming/Validating the Uncore," M. Wachs. C2S2 Annual Review Presentation 2010 (Slides in pdf format)
"Rethinking Digital Design: Why Design Must Change," O. Shacham, O. Azizi, M. Wachs, W. Qadeer, Z. Asgar, K. Kelley, J.P. Stevenson, A. Solomatnikov, A. Firoozshahian, B.C. Lee, S. Richardson, M. Horowitz. IEEE Micro, Nov/Dec 2010. (IEEE Explore or IEEE Computer Society)