Table of Contents FFT Generator FFT VLSI_SoC Paper - Algorithm Formal Proof FFT VLSI_SoC Paper - Errata Figures 3-5: Incorrect order for Stage 1 reads and writes

The FFT generator should be available on at least one of the following links:

• http://www-vlsi.stanford.edu:8080
• http://www-vlsi.stanford.edu/genesis
• http://www-vlsi.stanford.edu:8081

• vlsiweb: 8080 genesis 8081 8082 8083

Formal proof (under construction) can be found here: http://genesis2.stanford.edu/mediawiki/index.php/FFT_Formal_Proof

Figures 3-5 show the following read pattern for stage 1:

• cycle 4 reads dp0,dp2; cycle 5 reads dp1,dp3; cycle 6 reads dp2,dp4; cycle 7 reads dp5,dp7

This is incorrect. The correct read pattern should be as follows:

• cycle 4 reads dp0,dp2; cycle 5 reads DP2,DP4; cycle 6 reads DP1,DP3; cycle 7 reads dp5,dp7

Writes must be adjusted as necessary to follow the reads.