Teguh Notes (in org-mode as usual):

General Notes:

• Please merge all timelines in a group to have a timeline for the entire group so rollups can be presented as a group rather than individuals in the group

For Discussion:

• Should Peak be decoupled from the other tools (by collateral possibly) so the other tools can start working with some information that doesn’t come directly out of Peak?
• Floating point formal verification? What would be useful? Possibly to verify correctness of rewrite rules on an abstracted version of floating point that is not as tricky for hardware?
• Garnet
• Third-Party IP Protection
• Power Domains

• program to generate random halide pipelines
• Feb 8 - goal is to generate 1000 random halide functions
• Mar 1? - camera pipeline from raw to rgb
• people working on halide have the ability to make random DAGs of various primitives in varying degrees of complexity to push through the rest of the flow
• Priyanka wants a bitstream through garnet by Mar 1

• Anything beyond what was just said
• There will only be DAGs of stencil pipelines, and a camera pipeline

• make sure that random pipeline generator can go through the compiler
• histogram, multiple pixels per cycle, multiple cycles per pixel, strided access
• merge linebuffer and doublebuffer implementations

• upsample/downsample

• Need elements to be added to CoreIR
• Need testing in CoreIR

• floating point specification in CoreIR
• aiming to specify the PE tiles in Peak
• API for manually writing mapper rules
• Automatic mapper generation from Peak
• Integrate FPGen with CoreIR ops
• Garnet is aiming to support three DSLs: Peak, Interconnect, and Memory
• Want to figure out the best interconnect design based on the 1000 halide applications that will be generated
• Implement all the garnet passes to better support power domains and other physical design problems instead of having them hardcoded
• Get functional specification out of Peak and compile to magma

• Ross wants reduces out of the halide compiler in a specific optimized form
• Needs code from Nikhil for the divide operation
• Needs to work to figure out what the PE spec is and how to use Peak to create it
• Need to be able to peek internal signals in magma

• Meet with all designers and determine what good blocks for testing are what what good blocks for verification are
• Faster SMT solving specced out
• Transition system text format for CVC4
• SQED for accelerators, examined on a 4x4 CGRA as proof of concept
• contract-based verification to embed smt-based description in coreir metadata
• floating point formal verification?

• Need CoreIR metadata to support passing through SMT info

• Meet with designers to figure out how to get more useful tests and what things would be good to test
• Set up CI infrastucture with commercial tool support
• Any new RTL needs to have 90% line coverage or pull request will be blocked
• Constrained random
• Interactive mode using verilog DPI for easier debugging
• Porting testbench generator to Fault
• testing hackathon

• Might need dead-code elimination in CoreIR
• Would like others to start adding their test plans (in English) in the Garnet repo

• 90% coverage only on the things that can change as determined by formal verification

• cgra-soc interface
• soc integration
• zynq prototype for the soc
• software architecture proposal
• soc configuration protocol

• talk with pnr and compiler about information that needs to be added into the configuration
  • done signal from cgra
  • bank information for second level memory
• cgra and soc need to agree on interface

• next version of the PE with floating point and transcendentals
• memory tile with test-driven design, with ability to use as double buffer
• new interconnect
• 2nd level memory hierarchy
• column-wise global signals
• double-buffering of config registers
• column-wise control of power domains (at the application level for this quarter)
• virtual tapeout bimonthly

• where to put the done signal
• need information about latency and input size from compiler
• pnr needs to have power domain information
• coreir needs to output power domain information
• mapper and pnr should be aware of power domain and signals crossing power domains
• generator in upf files