FETCH

Goal: read next instruction out of memory and write it into Instruction Register

• Remember: PC is always pointing to address of next instruction

Register Transfer Notation

IR <== Mem[(PC)]

1. Take contents of PC, put it on bus, and put it onto MAR
2. Read out of memory
3. Write it into the IR

Control Instructions

1. Gate.PC - Puts contents of PC onto the bus
2. LD.MAR - Writes into the MAR
3. MEM.EN - Enable memory write/read (also wait for R)
4. MDRMUX - Not shown in diagram, but there's actually a mux to determine where to write into MDR from
5. LD.MDR - Load memory into MDR
6. Gate.MDR - Write memory onto main bus
7. LD.IR - Write data into IR

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ADD

Register Transfer Notation

DR <== (SR1) + (SR2)

Control Instructions

1. SR1MUX selects IR[8:6]
2. SR2MUX selects SR2OUT
3. ALUK selects ADD - Tells ALU which operation to do
4. GateALU - Opens data into bus
5. DRMUX selects IR[11:9]
6. LD.REG - Write into Register
7. LD.CC

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AND

DR <== (SR1)(SR2)

Basically, add but instead of selecting ADD with ALUK you select AND

Control Instructions

1. SR1MUX selects IR[8:6]
2. SR2MUX selects SR2OUT
3. ALUK selects AND - Tells ALU which operation to do
4. GateALU - Opens data into bus
5. DRMUX selects IR[11:9]
6. LD.REG - Write into Register
7. LD.CC

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NOT

Register Transfer Notation

DR <== (SR')

Control Instructions

1. SR1MUX selects IR[8:6]
2. ALUK selects NOT - tells ALU which operation to do
3. Gate.ALU - lets data from ALU onto bus
4. DRMUX selects IR[11:9]
5. LD.REG - write data from bus into register
6. LD.CC

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LEA

Loading an effective address (never accessing memory) and writing that into the destination register

Register Transfer Notation

DR <= (PC) + SEXT(IR[8:0])

Control Instructions

1. ADDR1MUX selects PC - Don't want to send data through bus, just select wire coming from PC
2. ADDR2MUX selects IR[8:0] - Remember PCOffset9
3. MARMUX selects ADDR ADD - Select output from ADDR
4. Gate.MARMUX - Open gate from ADDR onto bus
5. DRMUX selects IR[11:9]
6. LD.REG - Write into register

Remember, we do not do LD.CC for this one!

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JUMP

We are now into control instructions! They all write into PC because they change where our next instruction is in memory

Register Transfer Notation

PC <= (BaseR)

Control Instructions

1. SR1MUX selects IR[8:6]
2. ADDR1MUX selects SR1OUT - we don't actually want to add but we pass it through
3. ADDR2MUX selects 0 - just pass through content
4. PCMUX selects ADDR ADD - want to select output from adder
5. LD.PC - Load data into PC

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LD

Very similar to LEA but now we want to access memory

Register Transfer Notation

DR <= Mem[(PC) + SEXT(IR[8:0])]

Control Instructions

1. ADDR1MUX selects PC
2. ADDR2MUX selects SEXT([IR8:0])
3. MARMUX selects ADDR ADD
4. Gate.MARMUX opens to let data from MARMUX onto bus
5. LD.MAR - Load data into MAR
6. MEM.EN/R - Enable memory read/write
7. MDRMUX selects Memory
8. LD.MDR - Load data into MDR
9. Gate.MDR - Open to let data onto bus
10. DRMUX selects [11:9]
11. LD.REG - Load data into register
12. LD.CC

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ST

Register Transfer Notation

Mem[(PC) + SEXT([IR8:0])] <= SR

Writing data from a source register into memory at the location of an effective address (we get using PC relative addressing)

First thing, calculate effective address, then write into memory

Control Instructions

1. ADDR1MUX selects PC - send PC into ADDR
2. ADDR2MUX selects SEXT([IR8:0]) - Sign extension
3. MARMUX selects ADDR ADD
4. Gate.MARMUX - sends data onto bus
5. LD.MAR - Load data from bus onto MAR

Now, we got our address put into memory to say where we wanna access. Then, set up source register data so we can write it into memory. Goal: source register to MDR

6. SR1MUX selects IR[11:9] - Data from source register is found in bits 11 through 9
7. ALUK selects Pass Through - puts data from SR1 onto bus
8. Gate.ALU - let data onto bus
9. MDRMUX selects bus - let data from bus onto the MDR
10. LD.MDR - load data into MDR

Now, we have our data in MDR and our address in MAR, so we can just write it into memory

11. MEM.EN W - write data into memory

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LDR

Register Transfer Notation DR <= Mem[(IR[8:6]) + SEXT(IR[5:0])]

Control Instructions

1. SR1MUX selects IR[8:6]
2. ADDR1MUX selects SR1OUT
3. ADDR2MUX selects SEXT(IR[5:0]) - add offset6
4. MARMUX selects ADDR ADD
5. Gate.MARMUX - open gate to let data onto bus
6. LD.MAR - Write into MAR
7. MEM.EN R - Write into memory
8. MDRMUX selects memory
9. LD.MDR - Load into MDR
10. Gate.MDR - Open gate to let data from MDR onto bus
11. DRMUX selects IR[11:9]
12. LD.REG - Load into register
13. LD.CC

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STR

Register Transfer Notation

Mem[(IR[8:6]) + SEXT[IR[5:0]]] <= SR

Control Instructions

1. SR1MUX selects IR[8:6]
2. ADDR1MUX selects SR1OUT
3. ADDR2MUX selects SEXT(IR[5:0])
4. MARMUX selects ADDR ADD
5. Gate.MARMUX
6. LD.MAR

Clock 2

7. SR1MUX selects IR[11:9]
8. ALUK selects Pass Through
9. Gate.ALU
10. MDRMUX selects Bus
11. LD.MDR

Clock 3 12. MEM.EN W

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LDI

Register Transfer Notation DR <= Mem[Mem[(PC) + SEXT(IR[8:0]))]]

Control Instructions

1. ADDR1MUX selects PC
2. ADDR2MUX selects SEXT(IR[8:0]) - PCOffset9
3. MARMUX selects ADDR ADD
4. Gate.MARMUX
5. LD.MAR

Cycle 2

6. MEM.EN R - Read memory into MDR
7. MDRMUX selects Memory
8. LD.MDR

Cycle 3

9. Gate.MDR
10. LD.MAR

Cycle 4

11. MEM.EN R
12. MDRMUX selects Memory
13. LD.MDR

Cycle 5

14. Gate.MDR
15. DRMUX selects IR[11:9]
16. LD.REG
17. LD.CC

STI

Register Transfer Notation Mem[Mem[(PC) + SEXT(IR[8:0]))]] <= SR

Control Instructions

1. ADDR1MUX selects PC
2. ADDR2MUX selects SEXT(IR[8:0]) - PCOffset9
3. MARMUX selects ADDR ADD
4. Gate.MARMUX
5. LD.MAR

Cycle 2

6. MEM.EN R - Read memory into MDR
7. MDRMUX selects Memory
8. LD.MDR

Cycle 3

9. Gate.MDR
10. LD.MAR

Cycle 4

11. SR1MUX selects IR[11:9]
12. ALUK selects Pass Through
13. Gate.ALUK
14. MDRMUX selects Bus
15. LD.MDR

Cycle 5

16. MEM.EN W