L07 [The LC-3 Part II]

Instruction Set Architecture (ISA)

The ISA specifies all the information about the computer that the software needs to be aware of

• Programmer's view of the CPU
• The internal implementation of the LC-3 is the datapath and microcode

Who uses the ISA?

• Machine language programmers
• Assembly language programmers
• Compiler writers
• High-level language programmers interested in performance, debugging, etc.

What is specified in the ISA?

• Memory organization
• Registers
• Instruction set
  • Opcodes
  • Data types
  • Addressing modes

LC-3 Memory Organization

• Address Space
  • 16 bit address
  • 0 - 65535
  • 0x0 - 0xFFFF
• Addressability
  • 16 bits
• Word Addressable/Byte Addressable
  • Strictly word addressable with 16 bit words

There are 8 general purpose registers (R0 - R7). The PC is NOT considered a general purpose register (GPR).

**How many instructions? (ISA design philosophies)

Lots

• CISC (Complex Instruction Set Computer)
• Intel x86, DEC VAX, IBM Z-series
• Do as much as you can in a single instruction
• Relatively easy to write efficient machine code by hand

Few

• RISC (Reduced Instruction Set Computer)
• ARM, PowerPC, MIPS, LC-3
• Expose as much as you can to the compiler so that it can optimize
• Hard to write efficient machine code by hand

LC-3 Machine Code and Assembly Language

For now, we are focused on the LC-3 datapath

• The circuit implementation and the state machine
• The control signals that make each instruction happen

You will need to understand what each LC-3 machine code instruction does – atomically, in isolation

• What registers or memory locations does it change?
• Which ALU operation is happening?
• How does the data flow through each MUX and the bus to make the operation execute with the correct behavior?

You do NOT need to understand why or how you would use these instruction in a program just yet

• We'll cover that later with assembly
• For now, just understand each instruction's behavior – so you can know how to implement it in the datapath and microcode, using control signals

Meet the LC-3 Instruction Set

• 16-bit instructions
• 4 bits for opcodes (bits 15-12)
• How many instructions?
• 15 - code 1101 is reserved for future use

What makes the fetch-execute cycle happen?

• The FSM, which sequences through the states
• Turns on the appropriate control signals as it enters each state

**Addressing Modes (for ALU operations)

• Register
  • All operands come from register file
  • Examples: ADD R1, R2, R3
• Immediate or Literal
  • Some operands come from bits in the instruction itself (get them from the IR)
  • Immediate values are 5-bit two's complement (for ADD and AND)
    • From bits [0:4] in the instruction itself
  • Sign-extend the immediate value to 16 bits 2's complement
    • ADD R1, R2, #3

We use the term Effective Address to describe the memory location that the instruction uses for its operands.

Data Movement Instructions

Purpose: Load data into a register (usually from memory) and store a register's value out to memory

Addressing Mode (for memory)

Where can operands (data) be found?

1. In the instruction (literal or immediate)
2. In registers
3. In memory

Can we fit a full memory address in a machine instruction?

• No, because we need some bits for the op code and other parts of the instruction

Addressing Modes

• Immediate or literal
• Register
• PC-relative *
  • PC-relative is a historical term; the mode acts like PC + Offset
• Base + Offset *
• Indirect *

• These 3 addressing modes involve memory locations, at the effective address

Each instruction allows a subset of these addressing modes (a common approach in RISC architecture)

• Imagine memory is a large array
  • int mem[65536]
• Calculate the effective address (EA), based on the addressing mode
  • PC relative
    • mem[PC + offset]
  • Base + Offset
    • mem[BaseReg + offset]
  • Indirect
    • mem[mem[PC + offset]]

Calculate a PC-Relative Effective Address

• Calculate 16-bit memory address by adding an offset value in the instruction itself (as two's complement)

For example, we can include a 9-bit offset value in the instruction itself (2's complement)

• Can represent values from -256 to +255
• Let's call this value PCoffset9

We can add PCoffset9 to the PC value (or a register value)

• But first we have to sign extend PCOffset9 to 16 bits

Because of the ISA design of the LC-3, we only discuss addressing modes and effective addresses for the last operand

• Each operand but the last always uses register addressing mode and the Effective Address is always the named register

Data Movement Instructions

• Data movement instructions move
• Memory to a register
• A register to memory

The basic format is

Op	DR or SR	Address generation bits

Load from Memory: 3+ cycles

1. Send the address to MAR
2. Read memory[MAR] into MDR
3. Send MDR back to a register]

Data Movement Instructions

• Base + Offset
  • 6 bit 2's complement for offset

For base offset, the only thing you change is the ADDR2MUX and instead of adding PC, add from SR1

For indirect mode,

• LDI+ (Load Indirect)
  • Starts off like base offset
  • Copy MDR to MAR to get our new address
  • Same final state
  • You add two more states (so 5 states to do LDI+)
  • Start of like same first two states of LD, read memory, but then after reading memory, the new 3rd state is copy MDR to MAR and then 4th state is read memory into MDR, and then the final state is the same
• STI
  • Also 5 states

All the other loads take 3 states!

Immediate Mode

LEA: There is no memory access! All we have to do is calculate the effective address, but instead of copying into the MAR, we can just copy it straight into DR (Data Register)

• There is only 1 cycle

Compare and Constrast

• LEA
  • DR <- PC + Offset9
  • Puts the effective address (PC + offset) itself into a register! (No memory access)
• LD
  • DR <- Mem[PC + PCOffset9]
  • Puts contents of some memory at the effective address (PC + offset) into a register
• LDI
  • DR <- Mem[Mem[PC + PCOffset9]]
  • Goes to the effective value and gets a value. Treats that value as another memory address, gets data from there, and moves it into a register (hits memory twice)
• LDR
  • DR <- Mem[BaseR + Offset6]
  • Puts the contents of the effective address (base register + offset) into a register

Store to Memory

1. Send address to MAR
2. Send the data to MDR
3. Store MDR into memory

ST: Puts the contents of a register into memory at the effective address (PC+offset).

STR: Puts the contents of a register into memory at the effective address (base register+offset)

STI: Puts the contents of a register into a memory location whose address is stored in memory at the effective address (PC+offset). (Hits memory twice!)

Also, don't forget PC is always + 1

JMP R3

Set the value of the next address in the PC

• The default setter on the PCMUX is the +1 (PCMUX = 2), but you can toggle it to come from the bus
• There's another data path to move from SR1 to ADDR1MUX, add 0 into ADDR2Mux, and then move it to PCMux

Control Instructions (Part I)

1. JMP (jump)

• Set PC to contents of BaseR

2. BR (branch)

• Add offset to PC if condition matches

3. JSR
4. JSRR (return)

• Save PC in R7, then add PCOffset11 or set to BaseR

Attendance Quiz

Today's number is 16,841

Which instructions use the Base + Offset addressing mode?

• LDR, STR

Condition Codes

• N = Negative
• Z = Zero
• P = Positive

Basically, what is the status of the last number I put on the bus?

Z is just NOR everything

N is just first bit

P is just not positive and not negative

Recitation 9/22/2021

LC-3 Components

The black wire that wraps around everything is called the bus

• The bus is only allowed to have one value on it at a time (otherwise you will get a short)

Control Signals

• LD.__ is write
  • All the components that start with LD (load) are connected to things that store data (registers)
• gate___ is tri-state buffer
• __MUX is a selector for a multiplexor

Every row of LC-3 can store 16 bits, so the addressability is 16 bits. There are 16 bits to store the address itself, so there are 2^16 address spaces

RAM

You can assume that the address is one the bus. To access that address, load it into the MAR (first enabling LDMAR). Once it's in the memory address register, you have to enable memory. If you want to read/write turn on MEM.EN (MEM.EN = memory enable). After, you can turn on LD.MDR which loads it into the memory data register. If you want to write, turn on MEM.WE = Memory Write enable

This means

• MEM.EN is necessary to turn on for any memory access
• MEM.WE is necessary to turn on for any writes

Program Counter and Instruction Register

The PC holds the address of the next instruction, while the IR holds the value of the current instruction.

There are three ways to offset PC

1. PC + offset
2. PC + 1
3. Given a value for the PC via the bus

The "correct" way to offset PC is selected through PCMux

For the IR, a new value can be read from the bus (with signal LD.IR) and the current value is directly connected to relevant components.

Executing Instructions

Instruction execution has three stages called macrostates

• Each macrostate is made out of 1 or more microstates (1 per clock cycles)
• The microstates are the states in the microcontroller's state machine

Macrostates

1. Fetch (3 Clock Cycles)

• Load the instruction from PC
• Increment PC by one

2. Decode (1 Clock Cycle)

• The microcontroller looks at the instruction to figure out how to execute it

3. Execute (varies)

• The microcontroller steps through several microstates and asserts the correct control signals to execute the instruction