L06 [Von Neumann Model]

Exactly how did the FSM get that ADD instruction?

Before the FSM could execute the ADD instruction in the previous slides, it had to fetch the instruction from memory

• FETCH
• DECODE
• EXECUTE

The FSM fetches and decodes each instruction before it executes it.

What is a machine code program

• Series of machine code instructions
• Each instruction is a 16-bit data value
• The instructions are stored in memory
  • Usually in sequence
  • Consecutive memory locations

The Program Counter (PC) register holds the address of the next instruction to be executed

• Which line in the program am I at?

The Instruction Register (IR) holds the instruction currently being executed

PCMUX

• Adder to increment PC (+1)
• Data from bus to PC
• Data from effective address calculator to PC

Usually, you execute code line by line, but sometimes you need conditionals and loops, which is what the mux is for

LD.PC = write enable for PC

GatePC puts the PC value on the bus

Control Signals for PC Circuit

• GatePC (tri-state buffer)
• LD.PC (write enable for PC register)
• PC MUX (2 bit mux selector)
• 4 bits of control signal total

FETCH and DECODE

Fetch

• Takes 3 cycles to read data from memory

First the MAR is loaded with the contents of the PC.
Next, the memory is interrogated, which results
in the next instruction being placed by the memory into the MDR.
Finally, the IR is loaded with the contents of the MDR

Decode

• Takes 1 clock cycle
  • This is where the FSM generates the control signals for the specific instruction (such as ADD).

Total: 4 clock cycles (states) to fetch and decode an instruction

Machine Code Instruction Cycle

1. Fetch
2. Decode
3. Evaluate Address*
4. Fetch Operands*
5. Execute*
6. Store Result*

• = optional

ADD Instruction

ADD instruction only requires FETCH, DECODE, AND EXECUTE from the Machine Code Instruction Cycle.

Instruction Processing: FETCH

• Load next instruction (at next address stored in PC) from memory into Instruction Register (IR)
  • Copy contents of PC into MAR (Memory Address Register)
  • Send "read" signal to memory
  • Copy contents of MDR (Memory Data Register) into IR

Increment PC, so that it points to the next instruction in sequence

• PC becomes PC + 1

Instruction Processing: DECODE

• First, identify the opcode
  • On the LC-3, this is 4 bits [15:12].
  • The FSM chooses a next state corresponding to the desired opcode.
• Depending on opcode, identify the other operands from the remaining bits
  • Example:
    • for LDR, last six bits is offset
    • for ADD, last three bits is source operand #2
• Decode is THE finite state machine
  • It activates the control signals in the datapath.

Instruction Processing: EXECUTE

• Perform the operation, using the source operands
• Examples:
  • Send operands to ALU and assert ADD control signal
  • Do nothing (e.g., for loads and stores to memory – more on this later)

It depends

• Every instruction has a different execute phase with different control signals
• But every instruction starts with FETCH FETCH FETCH DECODE

Instruction Processing Review

Three kinds of basic instructions

• Computational Instructions (ADD, AND, NOT)
• Data Movement Instructions (LD, ST)
• Control Movement Instructions (JMP, BRnz)

The LC-3 is a Finite State Machine

• LC-3 Finite State Machine
  • Has 64 possible states
  • Orchestrates 42 control signals
    • Multiplexor selectors
    • Tri-state buffer enables
    • Register write-enables
    • Other control signals

What Makes the Fetch-Execute Cycle Happen?

• The FSM, which sequences through the states
• It turns on the appropriate control signals as it enters each state

Attendance Quiz 9/21/2021

Today's number is 48,360

When the Fetch-Execute cycle reaches the EXECUTE phase for an instruction, the PC contains of the word after the instruction being executed

• The next memory address is not always the next instruction we will execute (think conditionals or loops)