18. Signal Generators
18.1. _RMP_B
Type Function module
Input DIR: BOOL ( Direction, TRUE means Up )
E: BOOL ( Enable Input)
TR: TIME (time to run a full ramp)
I / O RMP: BYTE (output signal)
_RMP_B Is an 8-bit ramp generator. The ramp is generated in an externally
declared variable. The ramp is rising when DIR = TRUE and falling if DIR =
FALSE. Reaching a fnal value of the ramp, the generator remains at this
value. With the input E the ramp can be stopped at any time, when E =
TRUE the ramp runs. The input TR shows the time which is needed to cy-
cle through 0-255 or the other way around.
18.2. _RMP_NEXT
Type Function module
Input E: BOOL ( Enable Input)
IN: BOOL (input)
TR: TIME (rise time for ramp from 0255)
TF: TIME (fall time for ramp 2550)
TL: TIME (lock time between a change of direction)
I / O I/O
OUTPUT DIR: BOOL (direction of change in IN)
UP: BOOL (signals a rising ramp)
DN: BOOL (signals a falling ramp)
RMP_NEXT follows at the output OUT to the input signal IN with the in TR
and TF defned rising or falling fanks. Unlike RMP_SOFT the fank of
RMP_NEXT runs until it underrun or overrun the endpoint and is therefore
suitable for control tasks. Changing the value of IN so a rising ramp with
TR or a falling fank with TF starts at the output OUT until the value of OUT
has overrun or underrun the IN. The output then remains at this value. The
outputs of UP and DN shows just whether a rising or a falling edge are
created. The output DIR indicates the direction of change at IN, if IN is not
changed, the output remains at the last state. The lock time TL determi-
nes the delay time between the direction reversal.
The following graph shows the waveform at OUT when changing the input
signal at IN:
18.3. _RMP_W
Type Function module
Input DIR: BOOL ( Direction, TRUE means Up )
E: BOOL ( Enable Input)
TR: TIME (time to run a full ramp)
I / O RMP: WORD (output signal)
_RMP_B Is an 16-bit ramp generator. The ramp is generated in an external-
ly declared variable. The ramp is rising when DIR = TRUE and falling if DIR
= FALSE. Reaching a fnal value of the ramp, the generator remains at this
value. With the input E the ramp can be stopped at any time, when E =
TRUE the ramp runs. The input TR shows the time which is needed to cy-
cle through 0-65535 or the other way around.
18.4. GEN_PULSE
Type Function module
Input ENQ: BOOL ( Enable Input)
PTH: TIME (pulse duration HIGH)
PTL: TIME (pulse duration LOW)
Output Q: BOOL (output)
GEM_PULSE generates at the output Q, an output signal which sets in the
time of PTH to TRUE and then set for PTL to LOW. The generator will start
after ENQ = TRUE always with a rising edge at Q, and remains for the time
PTH to TURE. As long as ENQ = TRUE continuous pulses at the output Q
are generated. Is one of the times (PTH, PTL) or both equal to 0 the time
will limit to one PLC cycle. GEN_PULSE (ENQ: = TRUE, PTH: = T # 0s, PTL:
= T # 0s) generates an output signal which has one cycle TRUE and one
cycle FALSE. The Default ENQ value is TRUE.
18.5. GEN_PW2
Type Function module
Input ENQ: BOOL ( Enable Input)
TH1: TIME (set time HIGH when TS = LOW)
TL1: TIME (set time LOW when TS = LOW)
TH2: TIME (set time HIGH when TS = HIGH)
TL2: TIME (set time LOW when TS = HIGH)
TS: BOOL (selection for the end times)
Output Q: BOOL (binary output)
TL: TIME (elapsed time when Q = FALSE)
TH: TIME (elapsed time when Q = TRUE)
GEN_PW2 generates an output signal with a defnable time TH? for HIGH
and TL for LOW. Using the input TS is switched between two sets of para-
meters (TL1, TH1 and TL2, TH2). On startup or after a ENQ = TRUE, the
module begins with the LOW phase at the output.
18.6. GEN_RDM
Type Function module
Input PT: TIME (period time)
AM: REAL (signal amplitude)
OS: REAL (signal ofset)
Output Q: BOOL (binary output)
OUT: REAL (analog output signal)
GEN_RDM is a random signal generator. It generates the output OUT a
new value in PT intervals. The output Q is TRUE for one cycle when the
output OUT has changed. The input AM and OS set the amplitude and the
ofset for the output OUT. If the inputs OS and AM are not connected, then
the default values are 0 and.
The following example shows a trace recording of the input values PT =
100ms, AM = 10 and OS = 5. The output values generated every 100 ms
in the range of 0 10.
18.7. GEN_RDT
Type Function module
Input ENABLE: BOOL (enable input)
MIN_TIME_MS: TIME (Minimum cycle time)
MAX_TIME_MS: TIME (maximum cycle time)
TP_Q: TIME (pulse width of the output pulse to XQ)
Output XQ: BOOL (binary output)
GEN_RDT generates pulses with a defned pulse width and random spa-
cing. The output pulses with the pulse width TP_Q be generated at random
intervals TX. TX fuctuates randomly between time MIN_TIME_MS and
MAX_TIME_MS. The module generates output pulses at XQ only when the
ENABLE input is TRUE.
18.8. GEN_RMP
Type Function module
Input PT: TIME (period time)
AM: REAL (signal amplitude)
OS: REAL (signal ofset)
DL: REAL (signal delay 01 * PT )
Output Q: BOOL (binary output)
OUT: REAL (analog output)
GEN_RMP is a sawtooth generator. It generates a ramp at the output OUT
with the duration of PT and repeats this continuously. The output Q is for
exactly one cycle TRUE when the ramp starts at the output OUT. The input
AM and OS set the amplitude and the ofset for the output OUT. If the
inputs OS and AM are not connected the default values are 0 and 1. The
output OUT then generates a sawtooth signal of 0 1. The input DL can
move the output up to a period (PT) and is used to produce multiple
shifted signals to each other. A 0 at the input DL means no displacement.
A value between 0 and 1 shifts the signal by up to a period.
The following example shows a trace recording of the input values PT =
10s, AM = 1 and OS = 0
18.9. GEN_SIN
Type Function module
Input PT: TIME (period time)
AM: REAL (signal amplitude)
OS: REAL (signal ofset)
DL: REAL (signal delay 01 * PT )
Output Q: BOOL (binary output)
OUT: REAL (analog output)
GEN_SIN is a sine wave generator with programmable period, adjustable
amplitude and signal ofset. A special feature is a adjustable delay so that
with multiple generators overlapping signals can be generated. A Binary
Output Q passes a logical signal, which is generated phase equal to the
sine signal. The input DL is a delay for the output signal. The Delay is spe-
cifed with DL * PT. A DL of 0.5 delays the signal by half a period.
The following example shows GEN_SIN with a trace recording of the sine
signal and the binary output Q.
The above example generates a sine wave with 0.1 Hz (PT = 10 s) and a
lower peak value of 0 and upper peak value of 10.
18.10. GEN_SQR
Type Function module
Input PT: TIME (period time)
AM: REAL (signal amplitude)
OS: REAL (signal ofset)
DC: REAL (duty cycle 01)
DL: REAL (signal delay 01 * PT )
Output Q: BOOL (binary output)
OUT: REAL (analog output)
GEN_SQR is a sqare wave generator with programmable period, adjustable
amplitude and signal ofset and duty cycle DC ( Duty Cycle ). A special
feature is a adjustable delay so that with multiple generators overlapping
signals can be generated.
The following Example shows 2 GEN_SQR, one runs with a delay of 0.25 (¼
period). In the trace record clearly shows the signal of the frst generator
and the delayed signal of the second generator.
18.11. PWM_DC
Type Function module
Input F: REAL (output frequency)
DC: REAL (duty cycle 01)
Output Q: BOOL (output)
PWM_DC is a Duty - cycle modulated frequency generator. The generator
generates a fxed frequency F with a duty cycle (TON / TOFF) which can be
modulated (adjusted) by the input DC. A value of 0.5 at the input DC ge-
nerates a duty cycle of 50%.
The following image shows an output signal with a duty - cycle 2 / 1, which
corresponds to a DC (ratio) of 0.67.
18.12. PWM_PW
Type Function module
Input F: REAL (output frequency)
PW:TIME (pulse duration high )
Output Q: BOOL (output)
PWM_PW is a pulse width modulated frequency generator. The generator
generates a fxed frequency F with a duty cycle (TON / TOFF) which can
bemodulated (set) by the input PW. The input passes the time before the
signal remains TRUE.
18.13. RMP_B
Type Function module
Input SET: BOOL (set input)
PT: TIME (duration of a ramp 0255)
E: BOOL (enable input)
UP: BOOL (direction UP = TRUE means Up)
RST: BOOL (Reset input)
Output I/O
BUSY: BOOL (TRUE, when ramp is running)
HIGH: BOOL (maximum output value is reached)
LOW: BOOL (Minimum output value is reached)
RMP_B is a ramp generator with 8 bits (1 byte) resolution. The ramp of
0255 is divided into a maximum of 255 steps and go through, in a time
of PT once complete. An enable signal E switches the ramp generator on
or of. An asynchronous reset sets each time the output to 0, and a pulse
at the SET input sets the output to 255. With a UD input, the direction
OPEN (UD = TRUE) or down (UD = FALSE) is set. The output of BUSY =
TRUE indicates that a ramp is active. BUSY = FALSE means the output is
stable. The outputs HIGH and LOW are TRUE, if the output OUT reaches
the lower or upper limit (0 and 255).
At setting of PT has to be noted, that a PLC with 5ms cycle time needs
256*5 = 1275 milliseconds for a ramp. If the time PT is made shorter than
the cycle time multiplied by 256, the edge is translated in correspondingly
larger steps. The ramp is constructed in this case with less than 256 steps
per cycle. PT may be T#0s, then the output switched between minimum
and maximum value back and forth.
The following example shows an application of RMP_B. The outputs HIGH
and LOW triggers both NTSC (X4, X5) 1 second delayed, and switch with
the RS Flip Flop (X6) the UP input of the Ramps generators in order. The
result is a ramp of 5 seconds, followed by an break of 1 second and then
the reverse gradient of 5 seconds and then a break of 1 second. In the
Trace the history of the signals can be seen.
Timing diagram for Up / Down Ramp:
Another example shows the use of a sawtooth RMP_B.
Timing diagram for sawtooth:
18.14. RMP_SOFT
Type Function module
Input IN: BOOL (enable input)
VAL: Byte (maximum output value)
Setup PT_ON: TIME (rise time, Default is 100 ms)
PT_OFF: TIME (fall time; Default is 100 ms)
Output I/O
RMP_SOFT smooths the ramp of an input signal VAL. The signal Out follows
the input signal VAL, where increase time as well as fall time can be limi-
ted by PT_ON and PT_OFF. The rise time and fall time of the ramps are de-
fned by setup parameter in the module RMP_SOFT. The setup time PT_ON
specifes how long the ramp takes of 0255. A ramp that is limited by the
VAL, is accordingly shorter. PT_OFF defnes accordingly the falling ramp. If
the input IN is set to FALSE, VAL corresponds to a value of 0, so by swit-
ching the input IN between 0 and VAL it can be switched.
Example:
18.15. RMP_W
Type Function module
Input SET: BOOL (set input)
PT: TIME (duration of a ramp 065535)
E: BOOL (enable input)
UP: BOOL (direction UP = TRUE, means UP )
RST: BOOL (Reset input)
Output I/O
BUSY: BOOL (TRUE, when ramp is running)
HIGH: BOOL (maximum output value is reached)
LOW: BOOL (Minimum output value is reached)
RMP_W is a ramp generator with 16-bit (2 bytes) resolution. The ramp of
0 65535 is divided into a maximum of 65536 steps and run in a time of
PT once complete. An enable signal E switches the ramp generator on or
of. An asynchronous reset sets each time the output to 0, and a pulse at
the Set input sets the output to 65535. With the UD input, the direction UP
(UD = TRUE) or DOWN (UD = FALSE) is defned. The output of BUSY =
TRUE indicates that a ramp is active. BUSY = FALSE means the output is
stable. The outputs HIGH and LOW gets TRUE, the output OUT reaches the
lower or upper limit (0 and 65535).
At setting of PT is to be noted that a PLC with 5 ms cycle time needs
65536*5 = 327 seconds for a ramp. If the PT is the time defned shorter
than the cycle time 65536, the edge is translated in correspondingly lar-
ger steps. The ramp is constructed in this case with less than 256 steps
per cycle. PT may be T#0s, then the output switched between minimum
and maximum value back and forth.
For a detailed description, see the module RMP_B. The function is absolu-
tely identical except that the output OUT 8-bit wide instead of 16 bit.