15. Pulse Generators
15.1. A_TRIG
Type Function module
Input IN: REAL (input signal)
RES: REAL (input change)
Output Q: BOOL (output)
D: REAL (last change of the input signal)
A_TRIG monitors an input value on change and every time when the input
value changes by more than RES, the module generates an output pulse
for a cycle so that the new value can be processed. At the same time, the
device remembers the current input value with which it compares with the
input IN at the next cycle. At the output D the diference between IN and
the stored value is displayed.
15.2. B_TRIG
Type Function module
Input CLK: BOOL (Input signal)
Output Q: BOOL (output)
The function module B_TRIG generates after a change of edge on the CLK
input an output pulse for exactly one PLC cycle. In contrast to the two
standard modules R_TRIG and F_TRIG that produce only at falling or rising
edge of a pulse, B_TRIG generates at falling and rising edge of an output
pulse.
15.3. CLICK_CNT
Type Function module
Input IN: BOOL (Input)
N: INT (number ofclicks ) to decode
TC: TIME (time in which the clicks must take place)
Output Q: BOOL (output)
CLICK_CNT determines the number of pulses within the unit time TC. at in-
put IN. A rising edge at IN will start an internal timer with time TC. During
the course of Timers the module counts the falling edges of IN and review-
es after the expiry of the time TC whether N pulses are within the time TC.
Just when exactly N pluses within TC will happen, the output Q is set for a
PLC cycle to TRUE. The module decodes also N = 0, which corresponds to
a rising edge but not falling edge within TC.
15.4. CLICK_DEC
Type Function module
Input IN: BOOL (Input)
TC: TIME (time in which the clicks must take place)
Output Q0: BOOL (output signal rising edge
without falling edge)
Q1: BOOL (output signal of a pulse within TC)
Q2: BOOL (output signal for two pulses within TC)
Q3: BOOL (output signal for three pulses within TC)
CLICK_DEC decodes multiple keystrokes and signals to diferent outputs
the number of pulses. An input signal without falling edge within TC is is-
sued at Q0 and remains TRUE until IN goes on FALSE. A pulse followed by
a TRUE is output to Q1 and so on. Is a pulse registered within TC which is
followed by the state FALSE, then TRUE appear at the corresponding out-
put for a PLC cycle.
15.5. CLK_DIV
Type Function module
Input CLK: BOOL ( Clock Input)
RST: BOOL (Reset input)
Output Q0: BOOL (divider output CLK / 2)
Q1: BOOL (divider output CLK / 4)
Q2: BOOL (divider output CLK / 8)
Q3: BOOL (divider output CLK / 16)
Q4: BOOL (divider output CLK / 32)
Q5: BOOL (divider output CLK / 64)
Q6: BOOL (divider output CLK / 128)
Q7: BOOL (divider output CLK / 256)
The function module CLK_DIV is a divider module and devides the input si-
gnal CLK into 8 levels each divided by 2, so that at the output Q0 is half
the frequency of the input CLK with 50% duty cycle available. The output
Q1 is the halved frequency of Q0 available and so on, until at Q7 the input
frequency is divided by 256. A reset input RST sets asynchronous all out-
puts to FALSE. CLK is allowed to make only one cycle to TRUE, if CLK does
not this, CLK musst provided over TP_R.
The following example is a test circuit with a start signal via ENI / ENO
realized functionality. Figure 2 shows a corresponding trace recording of
the circuit:
15.6. CLK_N
Type Function module
Input N: INT ( Clock Divider)
Output Q: BOOL (clock output)
CLK_N generates a pulse every X milliseconds, based on the PLC internal 1
ms reference. The pulses are exactly one PLC cycle length and are genera-
ted every 2^N milliseconds.
The period is 1 ms for N = 0, 2ms for N = 1, 4ms, for N=2
CLK_N replaces the modules CLK_1ms, CLK_2ms, CLK_4ms and CLK_8ms
from older libraries.
The following picture shows the output signal for N=0:
15.7. CLK_PRG
Type Function module
Input PT: TIME (cycle time)
Output Q: BOOL (clock output)
CLK_PRG generates clock pulses with a programmable period PT. The out-
put pulses are only one PLC cycle.
15.8. CLK_PULSE
Type Function module
Input PT: TIME (cycle time)
N: INT (number of pulses to be generated)
RST: BOOL (Reset)
Output Q: BOOL (clock output)
CNT: INT (counter of output pulses)
RUN: BOOL (TRUE, if pulse generator is running)
CLK_PULSE generates a defned number of clock pulses with a program-
mable duty cycle. PT defnes the duty cycle and N is the number of gene-
rated pulses. WIth a reset input RST, the generator can be restarted at
any time. The output CNT counts the pulses generated and RUN = TRUE
indicates that the generator currently generate pulses. An input value N =
0 generates an infnite pulse series, the maximum number of pulses is li-
mited to 32767.
The following example shows an application of CLK_PULSE for the produc-
tion of 7 pulses with a duty cycle of 100 ms.
The trace recording, shows how the RESET (green) is inactive and thus
RUN (red) is active. The generator generates then 7 pulses (blue), as spe-
cifed at the input N. The output CNT counts from 1 on the frst pulse to 7
by the last pulse. After the end of the sequence RUN is inactive again and
the cycle is complete until it is started by a new reset.
15.9. CYCLE_4
Type Function module
Input E: BOOL ( Enable Input)
T0 _ T3: TIME (run time of each States )
S0: BOOL (continuous cycle Enable )
SX: INT ( State if SL = TRUE)
SL: BOOL (asynchronous Load input)
Output STATE: INT (status output)
CYCLE_4 generates theStates 03 if E = TRUE. The duration of each State
can be determined by the time constraints T0T3. The input SL starts
when TRUE from a predetermined STATE SX. The input E has the internal
Default = TRUE, so that it can also be left open. After a rising edge on E
the module always starts with STATE = 0, and if E = FALSE, the output
STATE remains at 0. With the input of S0 the cyclic mode is turned on, if S0
= FALSE the module stops at State = 3, if S0 = TRUE, the device begins to
State 3 again with State 0.
15.10. D_TRIG
Type Function module
Input IN: DWORD (input signal)
Output Q: BOOL (output)
X: DWORD (change of the input signal)
The function module D_ TRIG generates after a change at the input IN an
output pulse for exactly one PLC cycle. The module works similar to the
standard function blocks R_TRIG and F_TRIG and the library module
B_TRIG. While B_TRIG, R_TRIG and F_TRIG monitor a Boolean input, the
module D_TRIG triggers on any change in the DWORD-input IN. If the input
value has changed, the output Q for a PLC cycle is set to TRUE and the
output X indicates how much has changed in the IN input. The input and
output are of type DWORD. The input can also process WORD and BYTE
types. With output X it should be noted that DWORD is unsigned and
therefore a change of -1 at the input is not -1, but the number 2^32-2 at
the output. With the standard function DWORD_TO_INT the output X can
be converted to an integer, which displays also negative changes correctly.
The following example shows the application of D_TRIG when the input
changes value from 5 to 2:
15.11. GEN_BIT
Type Function module
Input IN0: DWORD (bit sequence for Q0)
IN1: DWORD (bit sequence for Q1)
IN2: DWORD (bit sequence for Q1)
IN3: DWORD (bit sequence for Q1)
CLK: BOOL (clock input)
STEPS: INT (number of generated clocks)
REP: INT
RST: BOOL
Output Q0: BOOL (bit sequence Q0)
Q1: BOOL (bit sequence Q1)
Q2: BOOL (bit sequence Q2)
Q3: BOOL (bit sequence Q3)
CNT: INT (number of output bits already generated)
RUN: BOOL (TRUE if the sequencer is running)
GEN_BIT is a fully programmable pattern generator. At the inputs in0 IN7
are the bit patterns at the input CLK in each case as a DWORD and passed
by each clock pulse to the outputs Q0 Q3 starting from bit 0 of ascen-
ding. After the frst clock pulse at the input CLK the output Q0 has bit 0 of
IN0 , at Q1 is bit 0 of In1 . on Q7 is bit 0 of IN3. After the next clock pulse
at the CLK input, the bit 1 of the inputs IN is passed to the outputs Q and
so on, until the sequence is completed. The input STEPS determines how
many bits of the input DWORDS be passed to the outputs. The input REP
determines how often this sequence is repeated. If the input set to 0, the
sequence is repeated continuously. An asynchronous reset can always re-
set the sequencer. The outputs CNT and RUN indicate which bit is current-
ly passed to the output and whether the sequencer is running, or the se-
quence (RUN inactive) has fnished. After the sequences have expired the
last bit patterns remains on the outputs available until a reset restarts the
generator.
Example:
In this example, the lowest 8 bits (bits 0 7) at the inputs IN are pushed
to the outputs Q. The sequence begins with bit 0 and ends at bit 7 (8
Steps are defned by the input 8). This sequence is repeated 2 times (2 re-
petitions at the input REP) and then stopped.
The Trace Recording shows the reset signal becoming inactive (green),
which starts the generator and after the frst clock pulse passes bit 0 to
the outputs.
15.12. GEN_SQ
Type Function module
Input PT: TIME (period time)
Output Q: BOOL (output)
Gen_SQ is a generator with programmable period time and a fxed duty
cycle of 50%. The input PT defnes the period time and the output Q pas-
ses the output signal.
15.13. SCHEDULER
Type Function module
Input E03: BOOL (release signal for Q03)
Setup T03: TIME (cycle time)
Output Q03: BOOL (output signals)
SCHEDULER is used to call time dependent program parts. For example,
complex calculations that are needed only rarely, can be called at fxed in-
tervals. The outputs Q? of the module will be active only for one cycle and
release the execution of the program part. The setup time T? specify at
which intervals the outputs are enabled. SCHEDULER checks per CPU cy-
cle only one output, so that in maximum one output per cycle can be acti-
ve. In the extreme case when all call times T? are T#0s, in each cycle one
output should be set, so that frst Q0, then Q1, etc. to Q3 are set and then
again to start Q0. The call times can therefore up to 3 CPU cycles and dif-
fer from the predetermined value T?.
15.14. SCHEDULER_2
Type Function module
Input E03: BOOL (release signal for Q03)
PT
Q
Setup C0 3: UINT (The output Q? is activated the C? cycles)
O0 3: UINT (delay for the outputs)
Output Q03: BOOL (output signals)
SCHEDULER_2 activates depending on the setup variables C? And O? The
outputs Q?. SCHEDULER_2 can an output Q? All C? cycles enable, to
launch the program items with diferent cycle times. An optional setup pa-
rameters O? is used to a time ofset of O? to defne cycles for the corre-
sponding output to a simultaneous turn of the outputs in the frst cycle to
prevent.
15.15. SEQUENCE_4
Type Function module
Input IN0 3: BOOL (enable signal for Q03)
START: BOOL (starting edge for the sequencer)
RST: BOOL (asynchronous reset input)
WAIT 03: TIME (wait for the input signal to 03)
DELAY 03: TIME (delay time until the input signal IN03 is
being tested)
Output Q 03: BOOL (control outputs)
QX: BOOL (TRUE if one of the outputs Q0Q3 is active)
RUN: BOOL (RUN is TRUE if the sequencer is running)
STEP: INT (indicates the current step)
STATUS: BYTE (to ESR compliant status output)
SEQUENCE_4 is a 4-bit sequencer with control inputs. After a rising edge
on START, RUN gets TRUE and the sequencer waits for the time Wait0 for a
TRUE signal at the input IN0. After the signal on IN0 is TRUE, the output
Q0 is set and waits the time Delay0. After the interval Delay0 in the next
cycle the module waiting the time wait1 for an input signal at in1 and Q0
remains TRUE, until Q1 is set. The whole procedure is repeated until all 4
cycles have elapsed. If during the waiting time wait03 the corresponding
input gets not true, an error is set, by corresponding Error Number at the
output STATUS it is displayed, and depending on the setup variable
STOP_ON_ERROR the sequencer is stopped or not. The STATUS output is
110 for waiting to the start signal, and 111 for pass through. It show the
sequence with 1 4 errors. A Error = 1 means that the signal at the input
in0 gets not active, a 2 corresponds to in1 etc.
The outputs RUN and STEP indicate whether the sequencer is running and
in which cycle it is at the moment. The output QX is TRUE, if one of the
outputs Q0Q3 are TRUE.
An asynchronous reset input can always reset the sequencer. This reset in-
put can also be connected with a output Q0Q3 to stop the sequencer be-
fore the full sequence. The sequencer can be started at any time with a ri-
sing edge on the START input, again and again. This is true, even if he has
not completed a sequence.
If not a edge examination of one or more inputs IN are required, they may
simply be left open, because the default value for this input is TRUE.
The initial state is compatible and ESR shows a value of 1-4 indicates that
an error has occurred. An error occurs if the corresponding input signal to
IN does not occur during the waiting period.
Error = 1 means that in0 is not within the waiting time has become active.
Error 2 4 corresponds to inputs 1 3.
A status value of 110 means on hold and 111 means that just a sequence
is running.
Example:
In the following Example is the sequencer is started with a rising edge.
Simultaneously, a pulse generator TP starts with 2 seconds, and that was
the starting trigger with 2 seconds delay to the input IN0. The sequencer
sets just after the start pulse, the output signal RUN and then waits for a
maximum of 5 seconds on a signal to IN0. The rising edge of IN0 that is
generated after 2 seconds of TP, Q0 is set and a delay for 1 second is
waited. This the frst step is fnished and the remaining steps are executed
without waiting for an input signal in 13. The default values for the inputs
IN are TRUE when they are unconnected.
The trace record shows the start signal (green) and the RUN signal (red).
After 2 seconds, the rising edge is putted on the input in0 and then on the
output signals Q03 and QX.
The signal QX (blue) is active if one of the output signals is active and the
RUN signal (red) is active from start to fnish.
15.16. SEQUENCE_64
Type Function module
Input START: BOOL (rising edge starts the sequence)
SMAX INT (last State the sequence)
PROG: ARRAY [063] OF TIME (duration of the individual states
)
RST: BOOL (asynchronous reset input)
Output STATE: INT ( State Output)
TRIG: BOOL (Indicates changes with condition TRUE)
SEQUENCE_64 generates a time sequence of up to 64 states. In the res-
ting state the output STATE is set to -1, thereby demonstrating to that the
module is not active. A rising edge at START starts the sequence and the
output switches to 0. After the waiting time PROG[0] the module switch
next to STATE = 1, waits the time PROG[1], switches to STATE = 2, etc.
until the output STATE reached the value of SMAX. After the waiting time
PROG[SMAX], the device returns to the idle state (STATE = -1). A change
to a new state STATE trigger of the output TRIG with a TRUE for one PLC
cycle. With TRIG easily downstream modules can be controlled. With the
input RST, the device can also be reset in the initial state at any time du-
ring the process of a sequence.
signal diagram of SEQUENCE_64:
15.17. SEQUENCE_8
Type Function module
Input IN07: BOOL (enable signal for Q07)
START: BOOL (starting edge for the sequencer)
RST: BOOL (asynchronous reset input)
WAIT 07: TIME (wait for the input signal to 07)
DELAY 07: TIME (delay time until the input signalIN07 tes-
ted)
Output Q 07: BOOL (control outputs)
QX: BOOL (TRUE if one of the outputs Q0 Q7 is active)
RUN: BOOL (RUN is TRUE if the sequencer is running)
STEP: INT (indicates the current step)
STATUS: BYTE (0 if no error, else > 0)
A functional description of SEQUENCE_8 can be found at SEQUENCE_4. SE-
QUENCE_8 function is identical with SEQUENCE_4. He has 8 instead of 4
channels. SEQUENCE_8 is used in the OSCAT library module Legionella.
15.18. TMAX
Type Function module
Input IN: BOOL (Input)
PT: TIME (switch of delay)
Output Q: BOOL (output)
Z: BOOL ( Trigger Output)
TMAX limits the duration of the output pulse to the time PT. The output Q
follows the input IN, as long as the TRUE time of IN is shorter than PT. If IN
is longer than PT to TRUE, the output pulse is shortened. Whenever an
output changes by a timeout to FALSE, the output Z is set to TRUE for a
cycle.
15.19. TMIN
Type Function module
Input IN: BOOL (Input)
PT: TIME (switch of delay)
Output Q: BOOL (output)
TMIN ensures that the output pulse Q is at least PT is set to TRUE, even if
the input pulse at IN is shorter than PT. otherwise the output Q follows the
input IN.
15.20. TOF_1
Type Function module
Input IN: BOOL (Input)
PT: TIME (switch of delay)
RST: BOOL (asynchronous reset)
Output Q: BOOL (output)
TOF_1 extended an input pulse at IN by the time PT. TOF_1 has the same
functionality as TOF from the standard LIB, but with an additional asyn-
chronous reset input.
15.21. TONOF
Type Function module
Input IN: BOOL (Input)
T1: TIME (ON Delay)
T2: TIME (OFF Delay)
Output Q: BOOL (output pulse)
TONOF creates a ON delay T1 and an OFF delay T2
The rising edge of the input signal IN is delayed by T1 and the falling edge
of IN is delayed by T2.
15.22. TP_1
Type Function module
Input IN: BOOL (Input)
PT: TIME (pulse duration)
RST: BOOL (asynchronous reset)
Output Q: BOOL (output pulse)
TP_1 is an edge-triggered pulse generator which generates a rising edge
at IN an output pulse at Q with the duration of PT. During the output pulse
an another rising edge to IN is created, the output pulse will be extended
so that after the last rising edge of output for the duration of PT remains
TRUE. The module can be reset at any time with a TRUE at the RST input.
Timing of TP_1:
15.23. TP_1D
Type Function module
Input IN: BOOL (Input)
PT1: TIME (pulse duration)
PTD: TIME ( Delay can be generated by new pulse)
RST: BOOL (asynchronous reset)
Output Q: BOOL (output pulse)
TP_1D is an edge-triggered pulse generator which generates at a rising
edge at IN an output pulse at Q with the duration of PT1. During the out-
put pulse an another rising edge to IN is created, the output pulse will be
extended so that after the last rising edge of output for the duration of PT
remains TRUE. After the end of the pulse duration PT1 the module block
the output for the time PTD. A new impulse can be restarted only after the
time PTD. The module can be reset at any time with a TRUE at the RST in-
put. The output W shows that the module in the waiting cycle, and as long
as W = TRUE, no new impuls can start.
15.24. TP_X
Type Function module
Input IN: BOOL (Input)
PT: TIME (pulse duration)
Output Q: BOOL (output pulse)
ET: TIME (Count the elapsed time of the output pulse)
TP_X is a multiple triggerable pulse generator. In contrast to the standard
module TP this template can be triggered multiple times and thus the out-
put pulse can be extended. The output Q remains after the last trigger
event (rising edge of IN) at ON, for the period of PT. While Q is true, by a
further edge at the IN the Timer can be triggered again and the output
pulse can be extended. In contrast to TOF, at TP_X the time PT is measu-
red as of the last rising edge, regardless of how long IN remains at TRUE.
This means that the output Q, after the time PT, is measured from the last
rising edge of IN moves to FALSE, even when the input IN is TRUE.
Timing of TP_X: