17. Latches, Flip-Flop and Shift Register.
17.1. COUNT_BR
Type Function module
Input SET: BOOL (Asynchronous Set)
IN: BYTE (default value for set)
UP: BOOL (forward switch edge-triggered)
DN: BOOL (reverse switch edge-triggered)
STEP: BYTE (increment of Counters )
MX: BYTE (maximum value of the Counters)
RST: BOOL (asynchronous reset)
Output CNT: BYTE (output)
COUNT_BR is a byte count from 0 to MX and starts again at 0. The counter
can, using two edge-triggered inputs UP and DN, both forward and back-
ward counting. when reaching a fnal value 0 or MX it counts again at 0 or
MX. The STEP input sets the increment value of the counter. With a TRUE
at input SET the counter is set to present value at the IN input. A reset in-
put RST resets the counter at any time to 0.
SET IN UP DN STEP RST CNT
Reset - - - - - 1 0
Set 1 N - - - 0 N
up 0 - ↑ 0 N 0 CNT + N
down 0 - 0 ↑ N 0 CNT - N
If the independent inputs UP and DN with CLK and a control input UP/DN
should be replaced, id can be done using two AND gates at the inputs:
COUNT_BR may work with individual step width at UP or Down command,
it is important to note that the counter behaves as if it internally counts
the number of STEP steps forward or backward.
Example:
MX = 50, STEP = 10
The counter will work as follows:
0,10,20,30,40,50,9,19 ,
Is 50 achieved in this example, it is recognized as a maximum value and it
continues counting from 0. Internally, it looks like this:
50,0,1,2,3,4,5,6,7,8,9 exactly 50 + 10 if after 50 the 0 comes back.
The implementation of a counter 0 50 in increments of ten is as follows:
MX = 59, STEP = 10 results in 0,10 .50,0,10
the transition from 50 to 0 is then exactly 10 steps.
17.2. COUNT_DR
Type Function module
Input SET: BOOL (Asynchronous Set)
IN: DWORD (default value for set)
UP: BOOL (forward switch edge-triggered)
DN: BOOL (reverse switch edge-triggered)
STEP: DWORD (increment of Counters)
MX: DWORD (maximum value of the Counters)
RST: BOOL (asynchronous reset)
Output CNT: DWORD (output)
COUNT_DR is a DWORD (32-bit) counter with counts from 0 to MX and
then begins again at 0. The counter can, using two edge-triggered inputs
UP and DN, both forward and backward counting. when reaching a fnal
value 0 or MX it counts again at 0 or MX. The STEP input sets the incre-
ment value of the counter. With a TRUE at input SET the counter is set to
present value at the IN input. A reset input RST resets the counter at any
time to 0.
SET IN UP DN STEP RST CNT
Reset - - - - - 1 0
Set 1 N - - - 0 N
up 0 - ↑ 0 N 0 CNT + N
down 0 - 0 ↑ N 0 CNT - N
If the independent inputs UP and DN with CLK and a control input UP/DN
should be replaced, id can be done using two AND gates at the inputs:
17.3. FF_D2E
Type Function module
Input D0: BOOL (Data 0 in)
D1: BOOL (Data 1 in)
CLK: BOOL (clock input)
RST: BOOL (asynchronous reset)
Output Q0 : BOOL (Data 0 out)
Q1 : BOOL (Data 1 out)
FF_D2E is a 2-bit edge-triggered D-Flip-Flop with asynchronous reset input.
The D-Flip-Flop stores the values at the input D at a rising edge at the CLK
input.
17.4. FF_D4E
Type Function module
Input D0: BOOL (Data 0 in)
D1: BOOL (Data 1 in)
D2: BOOL (Data 2 in)
D3: BOOL (Data 3 in)
CLK: BOOL (clock input)
RST: BOOL (asynchronous reset)
Output Q0 : BOOL (Data 0 Out)
Q1 : BOOL (Data 1 Out)
Q2 : BOOL (Data 2 Out)
Q3 : BOOL (Data 3 Out)
D1
D0
CLK
RST
Q1
Q0
FF_D2E is a 4-bit edge-triggered D-Flip-Flop with asynchronous reset input.
The D-Flip-Flop stores the values at the input D at a rising edge on CLK.
Detailed information can be found in the block FF_D2E.
17.5. FF_DRE
Type Function module
Input SET: BOOL (Asynchronous Set)
D: BOOL (Data in)
CLK: BOOL (clock input)
RST: BOOL (asynchronous reset)
Output Q : BOOL (Data Out)
FF_DRE is a edge-triggered D-Flip-Flop with Asynchronous Set and Reset
input. A rising edge at CLK stores the input D to output Q. A TRUE on the
SET or RST input resets or clears the output Q at any time regardless of
CLK. The reset input has priority over the input set. If both are active
(TRUE) are reset is processed and SET is ignored.
17.6. FF_JKE
Type Function module
Input SET: BOOL (Asynchronous Set)
J: BOOL (clock synchronous Set)
CLK: BOOL (clock input)
K: BOOL (clock synchronous reset)
RST: BOOL (asynchronous reset)
Output Q: BOOL (output)
FF_JKE is an edge-triggered JK-fop-fop with asynchronous Set and Reset
inputs. The JK-Flip-Flop sets the output Q when with a rising edge of the
CLK the Input J is TRUE. Q is FALSE when on a rising clock edge the input K
is TRUE. If the two inputs J and K on a rising clock edge are TRUE, the out-
put will be negated. It switches the output signal in each cycle.
D
CLK
RST
Q
SET
17.7. FF_RSE
Type Function module
Input CS: BOOL (edge-sensitive Set)
CR: BOOL (edge-sensitive reset)
RST: BOOL (asynchronous reset)
Output Q: BOOL (output)
FF_RSE an edge-triggered RS fip-fop. The output Q is set by a rising edge
of CS and cleared by a rising edge on CR. If both edges (CS and CR) rise at
the same time, the output is set to FALSE. An asynchronous reset input
RST sets the output at any time to FALSE.
17.8. LTCH
Type Function module
Input D: BOOL (Data in)
L : BOOL (Latch enable Signal)
RST: BOOL (asynchronous reset)
Output Q : BOOL (Data Out)
LTCH is a transparent storage element ( Latch ). As long as L is true, Q fol-
lows the input D and the falling edge of L stores the output Q the current
input signal to D. With the asynchronous reset input of the Latch will be
deleted at any time regardless of L.
17.9. LATCH4
Type Function module
Input D0 D3: BOOL (Data in)
L : BOOL (Latch enable Signal)
RST: BOOL (asynchronous reset)
Output Q0 Q3: BOOL (Data Out )
LTCH4 is a transparent storage element ( Latch ). As long as L is TRUE, Q0
- Q3 follows inputs D0 - D3 and with the falling edge of L the outputs Q0 -
Q3 stores the current input signal D0 - D3. With the asynchronous reset in-
L
RST
Q
SET
D
put of the Latch can be deleted at any time regardless of L. Further expla-
nations and details can be found in the module LTCH.
17.10. SELECT_8
Type Function module
Input E: BOOL ( Enable for outputs)
SET: BOOL (Asynchronous Set)
IN: BYTE (default value for set)
UP: BOOL (forward switch edge-triggered)
DN: BOOL (reverse switch edge-triggered)
RST: BOOL (asynchronous reset)
Output Q0 Q7: BOOL (outputs)
STATE: BYTE (status output)
SELECT_8 set only one output to TRUE as long as E = TRUE. The active
output Q0Q7 can be selected by the SET input and the value at the input
IN. A TRUE at SET and a value of 5 at the input IN set the output Q5 to
TRUE while all other outputs are set to FALSE. A TRUE at the input RST set
output Q0 to TRUE. With inputs UP is switched from an output Qn to Qn
+1, while the input DN switches an output Qn to Qn-1. The input EN must
be TRUE so that an output is TRUE, if EN is FALSE, all outputs are FALSE. A
FALSE at E does not afected the function of other inputs. Thus, even with
a FALSE at input EN can be switched up or down with UP or DN. The in-
puts UP and DN are edge-triggered and respond to the rising edge. The
state output always shows which output is currently selected.
E SET IN UP DN RST Q STATE
Reset X - - - - 1 Q0 if EN=1 0
Set X 1 N - - 0 QN if EN=1 N
up X 0 - ↑ 0 0 QN+1 if EN=1 N + 1
down X 0 - 0 ↑ 0 QN-1 if EN=1 N - 1
17.11. SHR_4E
Type Function module
Input SET: BOOL (Asynchronous Set)
D0: BOOL (Data Input)
CLK: BOOL (clock input)
RST: BOOL (asynchronous reset)
Output Q0: BOOL (Data Out 0)
Q1: BOOL (Data Out 1)
Q1: BOOL (Data Out 1)
Q3: BOOL (Data Out 3)
SHR_4E is a 4-bit shift register with asynchronous set and reset input. A ri-
sing edge at CLK, Q2 is moved to Q3, then moves the Q1 to Q2, Q0 to Q1
and D0 to Q0. With a TRUE on the Set input, all outputs (Q0 Q3) are set
to TRUE and with RST are all set to FALSE.
17.12. SHR_4UDE
Type Function module
Input SET: BOOL (Asynchronous Set)
D0: BOOL (Data Input Bit 0)
D3: BOOL (Data Input Bit 3)
CLK: BOOL (clock input)
DN: BOOL (control input Up / Down TRUE = D own )
RST: BOOL (asynchronous reset)
Output Q0: BOOL (Data Out 0)
Q1: BOOL (Data Out 1)
Q1: BOOL (Data Out 1)
Q3: BOOL (Data Out 3)
SHR_4UDE is a 4-bit shift register with Up / Down sliding directions. A ri-
sing edge at CLK, Q2 is moved to Q3, then moves the Q1 to Q2, Q0 to Q1
and D0 to Q0. The shift direction can be reversed with a TRUE at the input
DN, then the D3 is pushed to Q3 - to Q2 - to Q1 - to Q0. With a TRUE on
the Set input, all outputs (Q0 Q3) are set to TRUE and with RST all the in-
puts are set to FALSE.
17.13. SHR_8PLE
Type Function module
Input DIN: BOOL (Shift Data Input )
Dload: Byte (data word for parallel Load )
CLK: BOOL (clock input)
UP: BOOL (control input Up / Down, TRUE = Up )
LOAD: BOOL (control input for loading the register)
RST: BOOL (asynchronous reset)
Output DOUT: BOOL (Data Out )
SHR_8PLE is an 8 bit shift register with parallel Load and asynchronous re-
set. The shift direction can be reversed with the input of UP. When UP = 1,
bit 7 is frst pushed on DOUT and when UP = 0, bit 0 is frst pushed to
DOUT. For Up -Shift Bit 0 is loaded with DIN and Down - Shift Bit 7 is loa-
ded with DIN. At the input DLOAD one byte of data occures, which with
parallel Load ( LOAD = 1 and rising edge on CLK ) Is loaded into internal
registers. In the case of parallel Load is frst a shift done and then loaded
the register. An RST can always delete the register asynchronously. A de-
tailed description of a shift register, see the module SHR_4E.
17.14. SHR_8UDE
Type Function module
Input SET: BOOL (Asynchronous Set)
D0: BOOL (Data Input Bit 0)
D3: BOOL (Data Input Bit 3)
CLK: BOOL (clock input)
DN: BOOL (control input Up / Down, TRUE = Down )
RST: BOOL (asynchronous reset)
Output Q0 Q7: BOOL (Data Out )
SHR_8UDE is an 8 bit shift register with Up /Down sliding direction. A rising
edge at CLK, the data Q0 are be pushed to Q7 one step. Q0 is then loaded
with D0. The shift direction can be reversed with a TRUE at the input DN.
Then D7 is pushed to Q6, Q5, Q4, Q3, Q2, Q1, Q0 and Q7 is loaded with
D7. With a TRUE on the Set input, all outputs (Q0 Q3) set to TRUE and
RST all outputs are set to FALSE. Further explanation of shift registers, see
SHR_4E and especially at the module SHR_4UDE, which has the same
function for 4 bits as SHR_8UDE for 8 bits.
17.15. STORE_8
Type Function module
Input SET: BOOL (Asynchronous Set)
D0D7: BOOL (Data Input Bit 07)
CLR: BOOL (gradual reset input)
RST: BOOL (Asynchronous set input)
Output Q0Q7: BOOL (event outputs)
STORE_8 is an 8-event memory. A TRUE one of the inputs D0D7 sets the
corresponding output Q0 Q7. The asynchronous set and reset inputs
(SET, RST) set all outputs simultaneously to TRUE or FALSE. IF during a re-
set one of the inputs TRUE after the reset, the corresponding output is im-
mediately set to TRUE. If edge-triggered inputs are required, use TP_R mo-
dules before of the module STRORE_8. This allows the user to use both
edge triggered as well as condition-triggered inputs simultaneously. Input
CLR clears with a rising edge on CLR only one event, beginning with the
highest priority output that is just TRUE. If with CLR a output Q has clea-
red which input Q is TRUE, so the output D will be set to TRUE at the next
cycle.
17.16. TOGGLE
Type Function module
Input CLK: BOOL (clock input)
RST: BOOL (asynchronous reset)
Output Q: BOOL (output)
TOGGLE is a edge-triggered Toggle Flip -Flop with asynchronous reset
input. The TOGGLE Flip Flop invertes output Q on a rising edge of CLK. The
output changes on each rising edge of CLK his condition.