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#ARMSPI a packet based Serial-Peripheral-Interface (SPI) implementation for the stm32 line of IC's

General Principles

Interrupt based

The library is based around the ability of the Micro-controller to execute a specific piece of code, if an external event occurs, halting the main process during its execution. This enables a time efficient implementation of the otherwise wait-intensive communication protocols, especially if the other IC is not capable of sustaining the clock speeds theoretically possible with the master IC used.

Packet Based

The library abstracts the hardware through packets, making it possible to send and receive packets and letting the library handle the details. Because SPI is a synchronous protocol the packets are also kept in sync. This means that, as a Master, a received packet will always correspond to a sent one. This in turn means, that if an answer is longer than the packet sent, the answer will be spread over multiple packets in the receive buffer. Because of the fact, that the maximum length of receivable and sendable packets is the same, no Information is dropped. As a slave this means, that a sent packet will always correspond to a received one, all further bytes to be sent are ignored and therefor are irrelevant.

Fully buffered FIFO queue

The send and received packets are put in separate FIFO queues. This makes it possible to read from, and write to, the SPI without having to take care of timing it to the hardware. The structure is similar to this: +--------+ +-----------+ +---------- + +--------+ | TX-FKT | ---> | TX-packet | | RX-Packet | ---> | RX-FKT | +--------+ +-----------+ +---------- + +--------+ | TX-Packet | +=============+O-----------O+============+ | Rx-Packet | +-----------+ | SPI- |O-----------O| SPI- | +---------- + | TX-Packet | ---> | Hardware |O-----------O| Hardware | ---> | RX-Packet | +-----------+ +=============+ +============+ +---------- +