Mesaflash - PeterMue/ZX45-LinuxCNC GitHub Wiki

Synopsis

Mesaflash is the configuration and diagnostics command line tool for many Mesa boards. It's capabale of reading the current configuration but also writing a new configuration file onto the board.

There's a short info at https://mesaus.com/info/mesaflash.html

On a standard Debian LinuxCNC the tool should already be installed.

Otherwise it can be installed with

sudo apt-get update
sudo apt-get install mesaflash

Read board configuration info

To read the current boards configuration issue the following command mesaflash --device <YOUR DEVICE> --readhmid.

For my 5i25 with stock configuration this looks like:

peter@LinuxCNCNaN:~$ sudo mesaflash --device 6i25 --readhmid
[sudo] password for peter: 
Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA5I25
  FPGA Size: 9 KGates
  FPGA Pins: 144
  Number of IO Ports: 2
  Width of one I/O port: 17
  Clock Low frequency: 33.3333 MHz
  Clock High frequency: 200.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 33.333 MHz
  Register Stride: 258 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 2 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: QCount
  There are 2 of QCount in configuration
  Version: 2
  Registers: 5
  BaseAddress: 3000
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: StepGen
  There are 10 of StepGen in configuration
  Version: 2
  Registers: 10
  BaseAddress: 2000
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P3
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

1       0   IOPort       StepGen          0        Dir/Table2      (Out)
14      1   IOPort       StepGen          0        Step/Table1     (Out)
2       2   IOPort       StepGen          1        Dir/Table2      (Out)
15      3   IOPort       StepGen          1        Step/Table1     (Out)
3       4   IOPort       StepGen          2        Dir/Table2      (Out)
16      5   IOPort       StepGen          2        Step/Table1     (Out)
4       6   IOPort       StepGen          3        Dir/Table2      (Out)
17      7   IOPort       StepGen          3        Step/Table1     (Out)
5       8   IOPort       StepGen          4        Dir/Table2      (Out)
6       9   IOPort       StepGen          4        Step/Table1     (Out)
7      10   IOPort       SSerial          0        TXData1         (Out)
8      11   IOPort       SSerial          0        RXData1         (In)
9      12   IOPort       SSerial          0        TXData2         (Out)
10     13   IOPort       SSerial          0        RXData2         (In)
11     14   IOPort       QCount           0        Quad-IDX        (In)
12     15   IOPort       QCount           0        Quad-B          (In)
13     16   IOPort       QCount           0        Quad-A          (In)

IO Connections for P2
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

1      17   IOPort       StepGen          5        Dir/Table2      (Out)
14     18   IOPort       StepGen          5        Step/Table1     (Out)
2      19   IOPort       StepGen          6        Dir/Table2      (Out)
15     20   IOPort       StepGen          6        Step/Table1     (Out)
3      21   IOPort       StepGen          7        Dir/Table2      (Out)
16     22   IOPort       StepGen          7        Step/Table1     (Out)
4      23   IOPort       StepGen          8        Dir/Table2      (Out)
17     24   IOPort       StepGen          8        Step/Table1     (Out)
5      25   IOPort       StepGen          9        Dir/Table2      (Out)
6      26   IOPort       StepGen          9        Step/Table1     (Out)
7      27   IOPort       SSerial          0        TXData3         (Out)
8      28   IOPort       SSerial          0        RXData3         (In)
9      29   IOPort       SSerial          0        TXData4         (Out)
10     30   IOPort       SSerial          0        RXData4         (In)
11     31   IOPort       QCount           1        Quad-IDX        (In)
12     32   IOPort       QCount           1        Quad-B          (In)
13     33   IOPort       QCount           1        Quad-A          (In)

https://gist.github.com/PeterMue/c390a4d01559a251862511f920f12717

Write new bitfile

For my setup it's required to write a new bitfile to the 5i25. The setup consists of one 5i25 in combination with a 7i76 on P3 and a 7i85s on P2.

There are already some pre-compiled bitfiles for the 5i25 from mesa which can be found here: (Mesa Support Software)[http://www.mesanet.com/software/parallel/5i25.zip]

The zip contains also the source for the bitfiles which can be opend with Xilinx ISE.

We use the pre-built configuration named 5i25_7i76_7i85s.bit.

The 5i25 has two spaces for configurations: The userspace for the normal bitfile and a scond fallback space where a fallback bitfile resides. Everytime the userspace bitfile does not work properly, the card loads the fallback configuration and stays intact. This is important because the PCI implementation is part of this FPGA bitfile and if the one is broken it's impossible to communicate with the board (has to be re-programmed via the JTAG).

When we try to flash a new bitfile onto the board we first try it in the fallback region. Let's flash the new 5i25_7i76_7i85s.bit bitfile and try if it works.

peter@LinuxCNC-ZX45:~/linuxcnc/mesa/5i25/configs/hostmot2$ sudo mesaflash --device 5i25 --fallback --write 5i25_7i76_7i85s.bit 
Checking file... OK
  File type: BIT file
Boot sector OK
EEPROM sectors to write: 6, max sectors in area: 16
Erasing EEPROM sectors starting from 0x100000...
  |EEEEEE
Programming EEPROM sectors starting from 0x100000...
  |WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
Board configuration updated successfully.
Checking file... OK
  File type: BIT file
Boot sector OK
Verifying EEPROM sectors starting from 0x100000...
  |VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV
Board configuration verified successfully.

You must power cycle the hardware or use the --reload command to load a new firmware.

To load the new configuration from the fallback region we use the following command:

peter@LinuxCNC-ZX45:~/linuxcnc/mesa/5i25/configs/hostmot2$ sudo mesaflash --device 5i25 --fallback --reload
Waiting for FPGA configuration...OK

If everything works the output should look like above.

Now we can verify the configuration by running mesaflash --device 5i25 --readhmid. This should give us the new pinout configuration.

If the configuration works as expected we can flash the same file to the primary region. This is basically done the same way as before but without the --fallback parameter:

peter@LinuxCNC-ZX45:~/linuxcnc/mesa/5i25/configs/hostmot2$ sudo mesaflash --device 5i25 --write 5i25_7i76_7i85s.bit 

We can then reload the configuration by powering the card off and on or with mesaflash --device 5i25 --reload.

That's it!