chapter10 - PacoReinaCampo/PU-NTM GitHub Wiki

HARDWARE MODEL

CONCEPTUAL DESIGN PROCESS

The conceptual design process produces a high-level design concept that may be assessed to determine the potential for the resulting design implementation to meet the requirements. This may be accomplished using such items as functional block diagrams, design and architecture descriptions, circuit card assembly outlines, and chassis sketches.

Conceptual Design Objectives

The conceptual design objectives are:

The hardware item conceptual design is developed consistent with its requirements.
Derived requirements produced are fed back to the requirements capture or other appropriate processes.
Requirement omissions and errors are provided to the appropriate processes for resolution.

Conceptual Design Activities

Guidance for the conceptual design activities includes:

A high-level description should be generated for the hardware item. This may include:

a. Architectural constraints related to safety, including those necessary to address design errors and functional, component over-stress, reliability and robustness defects.

b. Identification of any implementation constraints on software or other system components.
Major components should be identified. The way they contribute to the hardware safety requirements should be determined, including the impact of unused functions.
Derived requirements, including the interface definition, should be fed back to the requirements capture process.
Requirement omissions and errors should be fed back to the appropriate process for resolution.
The reliability, maintenance and test features to be provided should be identified.

Note: Consensus between the relevant parties that the conceptual design objectives have been met is recommended. Typically, a design review is used to accomplish this consensus.

LANGUAGES

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VHDL Language

Overview

Normative references

Design entities and configurations

Subprograms and packages

Types

Declarations

Specifications

Names

Expressions

Sequential statements

Concurrent statements

Scope and visibility

Design units and their analysis

Elaboration and execution

Lexical elements

Predefined language environment

VHDL Procedural Interface overview

VHPI access functions

VHPI information model

VHPI tool execution

VHPI callbacks

VHPI value access and update

VHPI function reference

Standard tool directives

SystemVerilog Language

Overview

Normative references

Design and verification building blocks

Scheduling semantics

Lexical conventions

Data types

Aggregate data types

Classes

Processes

Assignment statements

Operators and expressions

Procedural programming statements

Tasks and functions (subroutines)

Clocking blocks

Interprocess synchronization and communication

Assertions

Checkers

Constrained random value generation

Functional coverage

Utility system tasks and system functions

Input/output system tasks and system functions

Compiler directives

Modules and hierarchy

Programs

Interfaces

Packages

Generate constructs

Gate-level and switch-level modeling

User-defined primitives

Specify blocks

Timing checks

Backannotation using the standard delay format

Configuring the contents of a design

Protected envelopes

Direct programming interface

Programming language interface (PLI/VPI) overview

VPI object model diagrams

VPI routine definitions

Assertion API

Code coverage control and API

Data read API