chapter10 - PacoReinaCampo/MPSoC-RISCV GitHub Wiki

HARDWARE MODEL

CONCEPTUAL DESIGN PROCESS

The conceptual design process produces a high-level design concept that may be assessed to determine the potential for the resulting design implementation to meet the requirements. This may be accomplished using such items as functional block diagrams, design and architecture descriptions, circuit card assembly outlines, and chassis sketches.

Conceptual Design Objectives

The conceptual design objectives are:

  1. The hardware item conceptual design is developed consistent with its requirements.

  2. Derived requirements produced are fed back to the requirements capture or other appropriate processes.

  3. Requirement omissions and errors are provided to the appropriate processes for resolution.

Conceptual Design Activities

Guidance for the conceptual design activities includes:

  1. A high-level description should be generated for the hardware item. This may include:

    1. Architectural constraints related to safety, including those necessary to address design errors and functional, component over-stress, reliability and robustness defects.

    2. Identification of any implementation constraints on software or other system components.

  2. Major components should be identified. The way they contribute to the hardware safety requirements should be determined, including the impact of unused functions.

  3. Derived requirements, including the interface definition, should be fed back to the requirements capture process.

  4. Requirement omissions and errors should be fed back to the appropriate process for resolution.

  5. The reliability, maintenance and test features to be provided should be identified.

    Note: Consensus between the relevant parties that the conceptual design objectives have been met is recommended. Typically, a design review is used to accomplish this consensus.

LANGUAGES

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VHDL Language

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Overview

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Normative references

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Design entities and configurations

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Subprograms and packages

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Types

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Declarations

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Specifications

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Names

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Expressions

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Sequential statements

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Concurrent statements

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Scope and visibility

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Design units and their analysis

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Elaboration and execution

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Lexical elements

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Predefined language environment

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VHDL Procedural Interface overview

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VHPI access functions

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VHPI information model

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VHPI tool execution

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VHPI callbacks

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VHPI value access and update

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VHPI function reference

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Standard tool directives

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SystemVerilog Language

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Overview

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Normative references

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Design and verification building blocks

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Scheduling semantics

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Lexical conventions

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Data types

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Aggregate data types

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Classes

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Processes

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Assignment statements

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Operators and expressions

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Procedural programming statements

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Tasks and functions (subroutines)

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Clocking blocks

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Interprocess synchronization and communication

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Assertions

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Checkers

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Constrained random value generation

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Functional coverage

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Utility system tasks and system functions

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Input/output system tasks and system functions

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Compiler directives

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Modules and hierarchy

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Programs

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Interfaces

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Packages

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Generate constructs

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Gate-level and switch-level modeling

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User-defined primitives

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Specify blocks

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Timing checks

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Backannotation using the standard delay format

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Configuring the contents of a design

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Protected envelopes

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Direct programming interface

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Programming language interface (PLI/VPI) overview

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VPI object model diagrams

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VPI routine definitions

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Assertion API

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Code coverage control and API

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Data read API

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