Rate Limiter - NetFPGA/OSNT-Public GitHub Wiki

Name

osnt_rate_limiter

Version

v1.00a

Author

Muhammad Shahbaz (shahbaz_at_cc.gatech.edu)

Type

pcore (HW)

Location

lib/hw/osnt/pcores/nf10_rate_limiter_v1_00_a/

Interface Types

AXI4-Stream

AXI4-Lite

Busses

S_AXIS_0: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 0

S_AXIS_1: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 1

S_AXIS_2: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 2

S_AXIS_3: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 3

S_AXIS_4: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 4

M_AXIS_0: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 0

M_AXIS_1: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 1

M_AXIS_2: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 2

M_AXIS_3: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 3

M_AXIS_4: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 4

S_AXI: Slave AXI4-Lite

Parameters

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

C_M/S_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

C_M/S_AXIS_TUSER_WIDTH: Data width of the TUSER.

C_NUM_QUEUES: Number of ports.

Register map

i = 0,1,2,3,4

C_BASEADDR + (i*0xC) + 0x0: Soft Reset (level sensitive)

C_BASEADDR + (i*0xC) + 0x4: Enable Rate Limiting

C_BASEADDR + (i*0xC) + 0x8: Rate in Bits

Description

This module limits the rate at which the packets can be sent through the egress interface(s). Current, implementation provides only few discrete set of values to choose the rate from (e.g., 10G/5G/2.5G and so on).