Pcap Replay - NetFPGA/OSNT-Public GitHub Wiki

Name

osnt_pcap_replay

Version

v1.00a

Author

Muhammad Shahbaz (shahbaz_at_cc.gatech.edu)

Type

pcore (HW)

Location

lib/hw/osnt/pcores/nf10_pcap_replay_v1_00_a/

Interface Types

AXI4-Stream

AXI4-Lite

Busses

S_AXIS: Slave AXI4-Stream bus, Variable width

M_AXIS_0: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 0

M_AXIS_1: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 1

M_AXIS_2: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 2

M_AXIS_3: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 3

S_AXI: Slave AXI4-Lite

Parameters

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

C_M/S_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

C_M/S_AXIS_TUSER_WIDTH: Data width of the TUSER.

C_NUM_QUEUES: Number of ports.

DST_PORT_POS: Position of destination port in TUSER.

Register map

i = 0,1,2,3

C_BASEADDR + 0x0: Soft Reset (level sensitive)

C_BASEADDR + [0x4-0x10]: Start Replay [0-3]

C_BASEADDR + [0x14-0x20]: Replay Count [0-3]

C_BASEADDR + [0x24-0x40]: Address Low & High [0-3]

C_BASEADDR + [0x44-0x50]: Soft Enable [0-3]

Description

The function of this block is to replay the traffic captured in the form of PCAP files. These PCAP files are stored in the on-board SRAMs, by the host. The replay engine reads the packets from these PCAP files and based on their destination port sends them out to the next module in the pipeline through the respective egress AXIS channel.