OSNT SUME Release Notes - NetFPGA/OSNT-Public GitHub Wiki

OSNT SUME v1.7.0

Updated the cores and tcl scripts for Xilinx Vivado 2016.4. Therefore, the tag version of the OSNT SUME repo works only for the Xilinx Vivado 2016.4.

OSNT SUME v1.6.0

Added a function to load a PCAP file with the timestamp in the file. List of updated cores and files.

• osnt_sume_extmem_pcap_replay_engine_v1_00
• generator.py
• generator_cli_lib.py
• osnt-tool-cmd.py
• gen_pcap_pkts.py

OSNT SUME v1.5.0

Added a project based on the external memory controller - OSNT-EXTMEM.

• OSNT SUME Aded IP cores
  • osnt_sume_extmem_pcap_replay_engine_v1_00 : External memory based pcap replay engine
  • osnt_sume_qdrA_v1_00: QDR-A memory controller
  • osnt_sume_qdrC_v1_00: QDR-C memory controller
  • osnt_sume_ddr3A_v1_00: DDR3-A memory controller
  • osnt_sume_ddr3B_v1_00: DDR3-B memory controller

OSNT SUME v1.4.0

Updated the hierarchy of the repository of the libraries and applications.

OSNT SUME v1.3.1

Added a pcap file generator for the test. Sorted out the archive of the app directory by separating gui, cli, and scripts for the OSNT SUME test suite. Check it out the app directory.

OSNT SUME v1.3.0

Add the command line interface for the generator, monitor, and latency measurements into the app directory, OSNT-SUME-live/util/app/gui.

Update the dma module and drive same with the SUME live.

Add a module for batching process to support capturing meta data at high data rate. Need to be integrated into the project.

• osnt_sume_batch_v1_00 : Batch process module.

OSNT SUME v1.2.0

Make it stable under anomaly condition. Updated and added the monitor pushing a small size of packets.

OSNT SUME v1.1.0

Updated the cores and projects with the Xilinx tool of Vivao version 2016.2.

OSNT SUME v1.0.0

The first OSNT SUME release! This release contains:

• Projects

  • OSNT SUME integrating generator and monitor

• OSNT SUME Standard Cores

  • osnt_sume_axi_sim_transactor_v1_00 : drives a Slave AXI-Lite for register read and write
  • osnt_sume_axis_sim_record_v1_00 : records traffic received from an AXI Stream master
  • osnt_sume_axis_sim_stim_v1_00 : drives an AXI Stream slave using stimuli
  • osnt_sume_bram_output_queues_v1_00 : BRAM-based output queues
  • osnt_sume_endianess_manager_v1_00 : packet byte endian manager
  • osnt_sume_input_arbiter_v1_00 : input arbitration
  • osnt_sume_nic_output_port_lookup_v1_00 : nic output port lookup
  • osnt_sume_output_queues_v1_00 : BRAM-based output queues
  • osnt_sume_riffa_dma_v1_00 : RIFFA-based DMA engine
  • osnt_sume_axi_if_v1_00 : register read and write test AXI4-Lite core
  • osnt_sume_common : common libraries for standard and osnt IP cores

• OSNT SUME IP cores

  • osnt_sume_10g_axi_if_v1_00 : 10G interface register access core for 10G interface block design
  • osnt_sume_10g_rx_queue_v1_00 : 10G interface rx queue core for 10G interface block design
  • osnt_sume_10g_tx_queue_v1_00 : 10G interface tx queue core for 10G interface block design
  • osnt_sume_bram_pcap_replay_uengine_v1_00 : BRAM-based pcap replay engine
  • osnt_sume_bram_v1_00 : BRAM AXI-Lite interface core
  • osnt_sume_extract_metadata_v1_00 : extract metadata
  • osnt_sume_inter_packet_delay_v1_00 : inter packet delay adjust
  • osnt_sume_monitoring_output_port_lookup_v1_00 : packet monitor lookup engine
  • osnt_sume_packet_cutter_v1_00 : packet cutter
  • osnt_sume_rate_limiter_v1_00 : pcap replay rate limiter
  • osnt_sume_timestamp_v1_00 : timestamp for rx and tx

• Tools

  • Based on the Xilinx tool of Vivao version 2014.4.
  • GUI : packet monitor and generator python GUI
  • pci_rescan_run: PCI bus rescan script, following FPGA reconfiguration

• For known issues please visit the following link:

https://github.com/NetFPGA/OSNT-SUME-live/issues

To avoid any issues, we recommend cloning the repo to a new folder.