Inter Packet Delay - NetFPGA/OSNT-Public GitHub Wiki

Name

osnt_inter_packet_delay

Version

v1.00a

Author

Muhammad Shahbaz (shahbaz_at_cc.gatech.edu)

Type

pcore (HW)

Location

lib/hw/osnt/pcores/nf10_inter_packet_delay_v1_00_a/

Interface Types

AXI4-Stream

AXI4-Lite

Busses

S_AXIS_0: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 0

S_AXIS_1: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 1

S_AXIS_2: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 2

S_AXIS_3: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 3

S_AXIS_4: Slave AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 4

M_AXIS_0: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 0

M_AXIS_1: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 1

M_AXIS_2: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 2

M_AXIS_3: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 3

M_AXIS_4: Master AXI4-Stream bus, Variable width, Enabled if C_NUM_QUEUES > 4

S_AXI: Slave AXI4-Lite

Parameters

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

C_M/S_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

C_M/S_AXIS_TUSER_WIDTH: Data width of the TUSER.

C_TUSER_TIMESTAMP_POS: Position of timestamp field in TUSER.

C_NUM_QUEUES: Number of ports.

Register map

i = 0,1,2,3,4

C_BASEADDR + (i*0x10) + 0x0: Soft Reset (level sensitive)

C_BASEADDR + (i*0x10) + 0x4: Soft Enable

C_BASEADDR + (i*0x10) + 0x8: Use Register Value (i.e., use delay value from a register instead of the one in TUSER)

C_BASEADDR + (i*0x10) + 0xC: Delay Register Value

Description

This block provides up to five instances of inter-packet-delays (e.g., four incase of NetFPGA-10G). This module adds necessary delay between packets either (1) calculated by the traffic model or (2) set by the host software as a fixed value. For (1), the traffic model appends the delay information as metadata on the packet. The extract_metadata module extracts this information and add it to the TUSER bits. The inter-packet-delay module reads this value from the incoming packet and set the timer accordingly. It then waits for the timer to expire before sending the nest packet. In case of (2), the host writes a fixed constant delay value in a register inside the delay module. The module reads this value and adds the requested delay between packets. Note that (2), if configured, has priority over (1).