1G MAC Interface v1.20 - NetFPGA/OSNT-Public GitHub Wiki
Name
osnt_1g_interface
Version
v1.20a
Type
pcore (HW)
Location
lib/hw/osnt/pcores/osnt_1g_interface_v1_20_a/
Interface Types
SGMII, AXI4-Stream, AXI4-Lite
Bus
M_AXIS_0, M_AXIS_1: Master AXI4-Stream (RX) bus, 8bit
S_AXIS_0, S_AXIS_1: Slave AXI4-Stream (TX) bus, 8bit
S_AXI: Slave AXI4-Lite
Parameters
C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream (RX) bus.
C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream (TX) bus.
C_BASEADDR: Base address value of the core.
C_HIGHADDR: High address value of the core.
Register map
0x0 : TX Timestamp enable (for portA and portB)
0x4 : Tx Timestamp offset for portA
0x8 : Tx Timestamp offset for portB
Description
This pcore is a combination of Xilinx Vitex-5 Embedded Tri-mode Ethernet MAC (TEMAC) and an AXI4-Stream adapter. Incoming SGMII signals from AEL2005 are received by the TEMAC and finally transformed into AXI4-Stream. The TX side follows the exact same path but in the opposite direction. Although we use "Tri-mode" MAC, due to the limitation of AEL2005, only Gigabit Ethernet mode is supported.
The Virtex-5 Embedded Tri-mode Ethernet MAC is a dual-MAC hard IP. Hence, each pore has two independent groups of buses, corresponding to each MAC.
There is one additional AXI4-Stream bus for transmitting bad_frame signal provided by Xilinx TEMAC. For more information about NetFPGA Standard IP Interfaces, please see here.