Register IO - NetFPGA/NetFPGA-public GitHub Wiki

Name

nf10_reg_io

Version

v1.00a

Author

Muhammad Shahbaz (muhammad.shahbaz_at_cl.cam.ac.uk)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/contrib/pcores/nf10_reg_io/

Interface Types

AXI4-Lite

Busses

S_AXI: Slave AXI4-Lite

Parameters

C_BAR0_BASEADDR: base address for the register inside the core.

C_BAR0_HIGHADDR: high address for the register inside the core.

C_BAR1_BASEADDR: base address for the table inside the core.

C_BAR1_HIGHADDR: high address for the table inside the core.

Register map

C_BAR0_BASEADDR + 0x00: Register 0

C_BAR0_BASEADDR + 0x04: Register 1

C_BAR0_BASEADDR + 0x08: Register 2

C_BAR0_BASEADDR + 0x0C: Register 3

C_BAR0_BASEADDR + 0x10: Register 2

C_BAR0_BASEADDR + 0x14: Register 3

C_BAR0_BASEADDR + 0x18: Register 0

C_BAR0_BASEADDR + 0x1C: Register 1

C_BAR1_BASEADDR + 0x00: Cell[Current Row Index][0]

C_BAR1_BASEADDR + 0x04: Cell[Current Row Index][1]

C_BAR1_BASEADDR + 0x08: Cell[Current Row Index][2]

C_BAR1_BASEADDR + 0x0C: Cell[Current Row Index][3]

C_BAR1_BASEADDR + 0x10: Current Row Index (Write)

C_BAR1_BASEADDR + 0x14: Current Row Index (Read)

Description

This blocks implements a sample design demonstrating how to instantiate and use generic register and table modules.