NetFlow simple 10G Bram - NetFPGA/NetFPGA-public GitHub Wiki

Name

netflow_simple_10g_bram

Location

contrib-projects/netflow_simple_10g_bram

Design Document

See the design document for the full documentation.

IP Cores

• Project Specific cores
  • netflow_cache
  • netflow_export
• NetFPGA-10G Specific cores
  • nf10_10g_interface
  • nf10_mdio
• Xilinx AXI Peripheral
  • axi_interconnect
  • axi_uartlite
  • axi_timebase_wdt
• Microblaze Subsystem
  • MicroBlaze
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block
  • proc_sys_reset
  • clock_generator
• Other
  • diff_input_buf

Description

This project captures the active flows received on a 10 Gbps Ethernet interface and exports them via other 10 Gbps Ethernet interface using the NetFlow v5 protocol. For more information see the design document.

Usage

1. Build the bitfile. Please read the README under projects/netflow_simple_10g_bram/ for detailed instructions. You can also use the pre-built bitfile supplied with the code to skip this step.
2. Follow Section 5 of the design document for testing the design.

Block Diagram

Please refer to the design document provided above for further details.