Refresh

This website github-wiki-see.page/m/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Reference-Manual-Appendix-B is currently offline. Cloudflare's Always Online™ shows a snapshot of this web page from the Internet Archive's Wayback Machine. To check for the live version, click Refresh.

NetFPGA 1G CML Reference Manual Appendix B - NetFPGA/NetFPGA-public GitHub Wiki

Table of Contents

  • Back to NetFPGA-1G-CML Reference Manual
  • [Appendix B: FPGA Pin Constraints] (#Top)
    • [System Clock and Reset] (#system-clock-and-reset)
    • [DDR3 SDRAM] (#ddr3-sdram)
    • [QDRII+] (#qdrii+)
    • [BPI Flash] (#bpi-flash)
    • [SD Card Connector] (#sd-card-connector)
    • [PCI Express] (#pci-express)
    • [Ethernet PHYS] (#ethernet-phys)
    • [PIC Interface] (#pic-interface)
    • [On-Board LED and Button I/O] (#on-board-led-and-button-io)
    • [PMOD Connectors] (#pmod-connectors)
    • [FMC Connector] (#fmc-connector)

Appendix B: FPGA Pin Constraints

The following list provides LOC and IOSTANDARD constraints for the main peripheral pins connected to the FPGA. This information can be used in a design UCF file with Xilinx ISE Design Suite, a design XDC file with Xilinx Vivado Design Suite, or with various interface generators included with Xilinx Coregen and MIG. Please see the Xilinx Constraints Guide (UG625) for ISE Design Suite based designs and Xilinx Vivado Design Suite User Guide: Using Constraints (UG903) for Vivado based designs.

Depending upon the design suite selected, this information can be expressed in either a UCF file or an XDC file as follows:

UCF format used with ISE Design Suite:

NET <port name> LOC=<io location> | IOSTANDARD=<io standard type>;

XDC format used with Vivado Design Suite:

set_property IOSTANDARD <io standard type> [get_ports { <port list> }]
set_property LOC <io location> [get_ports <port name>]

The information is presented in UCF format to express a clear association between the pin and the desired IO standard for the NetFPGA-1G-CML, although it can be readily translated into the XDC format. LOC information is provided here for all pins. IOSTANDARD information is provided for SelectIO pins. Other useful properties are suggested where appropriate.

Back to Top

System Clock and Reset

Port Name IO Location IO Standard Type
NET reset LOC = AA8 IOSTANDARD=LVCMOS18; # RESET button (BTN4)
NET system_clk_p LOC = AA3 IOSTANDARD=LVDS;
NET system_clk_n LOC = AA2 IOSTANDARD=LVDS;
Back to Top

DDR3 SDRAM

Port Name IO Location IO Standard Type
NET ddr3_dq[0] LOC = AE5 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[1] LOC = AE3 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[2] LOC = AD4 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[3] LOC = AF3 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[4] LOC = AE1 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[5] LOC = AF2 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[6] LOC = AD1 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[7] LOC = AE2 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_addr[0] LOC = Y3 IOSTANDARD = SSTL15;
NET ddr3_addr[1] LOC = Y2 IOSTANDARD = SSTL15;
NET ddr3_addr[2] LOC = W3 IOSTANDARD = SSTL15;
NET ddr3_addr[3] LOC = W5 IOSTANDARD = SSTL15;
NET ddr3_addr[4] LOC = AB2 IOSTANDARD = SSTL15;
NET ddr3_addr[5] LOC = W1 IOSTANDARD = SSTL15;
NET ddr3_addr[6] LOC = AC2 IOSTANDARD = SSTL15;
NET ddr3_addr[7] LOC = U2 IOSTANDARD = SSTL15;
NET ddr3_addr[8] LOC = AB1 IOSTANDARD = SSTL15;
NET ddr3_addr[9] LOC = V1 IOSTANDARD = SSTL15;
NET ddr3_addr[10] LOC = AD6 IOSTANDARD = SSTL15;
NET ddr3_addr[11] LOC = Y1 IOSTANDARD = SSTL15;
NET ddr3_addr[12] LOC = AC3 IOSTANDARD = SSTL15;
NET ddr3_addr[13] LOC = V2 IOSTANDARD = SSTL15;
NET ddr3_addr[14] LOC = AC1 IOSTANDARD = SSTL15;
NET ddr3_addr[15] LOC = AD5 IOSTANDARD = SSTL15;
NET ddr3_ba[0] LOC = AA5 IOSTANDARD = SSTL15;
NET ddr3_ba[1] LOC = AC4 IOSTANDARD = SSTL15;
NET ddr3_ba[2] LOC = V4 IOSTANDARD = SSTL15;
NET ddr3_ras_n LOC = Y6 IOSTANDARD = SSTL15;
NET ddr3_cas_n LOC = Y5 IOSTANDARD = SSTL15;
NET ddr3_we_n LOC = U5 IOSTANDARD = SSTL15;
NET ddr3_reset_n LOC = U1 IOSTANDARD = LVCMOS15;
NET ddr3_cke[0] LOC = AB5 IOSTANDARD = SSTL15;
NET ddr3_odt[0] LOC = U7 IOSTANDARD = SSTL15;
NET ddr3_cs_n[0] LOC = U6 IOSTANDARD = SSTL15;
NET ddr3_dm[0] LOC = AE6 IOSTANDARD = SSTL15;
NET ddr3_dqs_p[0] LOC = AF5 IOSTANDARD = DIFF_SSTL15_T_DCI;
NET ddr3_dqs_n[0] LOC = AF4 IOSTANDARD = DIFF_SSTL15_T_DCI;
NET ddr3_ck_p[0] LOC = AA4 IOSTANDARD = DIFF_SSTL15;
NET ddr3_ck_n[0] LOC = AB4 IOSTANDARD = DIFF_SSTL15;
Back to Top

QDRII+

Port Name IO Location IO Standard Type
NET qdriip_d[0] LOC = V8 IOSTANDARD = HSTL_I;
NET qdriip_d[1] LOC = V7 IOSTANDARD = HSTL_I;
NET qdriip_d[2] LOC = W9 IOSTANDARD = HSTL_I;
NET qdriip_d[3] LOC = Y11 IOSTANDARD = HSTL_I;
NET qdriip_d[4] LOC = Y8 IOSTANDARD = HSTL_I;
NET qdriip_d[5] LOC = Y7 IOSTANDARD = HSTL_I;
NET qdriip_d[6] LOC = W10 IOSTANDARD = HSTL_I;
NET qdriip_d[7] LOC = Y10 IOSTANDARD = HSTL_I;
NET qdriip_d[8] LOC = V9 IOSTANDARD = HSTL_I;
NET qdriip_d[9] LOC = AF8 IOSTANDARD = HSTL_I;
NET qdriip_d[10] LOC = AE8 IOSTANDARD = HSTL_I;
NET qdriip_d[11] LOC = AF9 IOSTANDARD = HSTL_I;
NET qdriip_d[12] LOC = AF10 IOSTANDARD = HSTL_I;
NET qdriip_d[13] LOC = AE10 IOSTANDARD = HSTL_I;
NET qdriip_d[14] LOC = AD10 IOSTANDARD = HSTL_I;
NET qdriip_d[15] LOC = AD11 IOSTANDARD = HSTL_I;
NET qdriip_d[16] LOC = AF13 IOSTANDARD = HSTL_I;
NET qdriip_d[17] LOC = AE13 IOSTANDARD = HSTL_I;
NET qdriip_q[0] LOC = AA14 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[1] LOC = AD14 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[2] LOC = Y15 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[3] LOC = AA15 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[4] LOC = AC14 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[5] LOC = AB14 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[6] LOC = Y16 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[7] LOC = AB15 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[8] LOC = AC16 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[9] LOC = AE20 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[10] LOC = AD19 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[11] LOC = AD18 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[12] LOC = AC19 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[13] LOC = AB20 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[14] LOC = AA20 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[15] LOC = AD20 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[16] LOC = AC17 IOSTANDARD = HSTL_I_DCI;
NET qdriip_q[17] LOC = AB17 IOSTANDARD = HSTL_I_DCI;
NET qdriip_sa[0] LOC = AC9 IOSTANDARD = HSTL_I;
NET qdriip_sa[1] LOC = AF7 IOSTANDARD = HSTL_I;
NET qdriip_sa[2] LOC = AA9 IOSTANDARD = HSTL_I;
NET qdriip_sa[3] LOC = AD8 IOSTANDARD = HSTL_I;
NET qdriip_sa[4] LOC = AC8 IOSTANDARD = HSTL_I;
NET qdriip_sa[5] LOC = AB7 IOSTANDARD = HSTL_I;
NET qdriip_sa[6] LOC = AB12 IOSTANDARD = HSTL_I;
NET qdriip_sa[7] LOC = AD13 IOSTANDARD = HSTL_I;
NET qdriip_sa[8] LOC = AC11 IOSTANDARD = HSTL_I;
NET qdriip_sa[9] LOC = AC12 IOSTANDARD = HSTL_I;
NET qdriip_sa[10] LOC = Y12 IOSTANDARD = HSTL_I;
NET qdriip_sa[11] LOC = AB11 IOSTANDARD = HSTL_I;
NET qdriip_sa[12] LOC = AB10 IOSTANDARD = HSTL_I;
NET qdriip_sa[13] LOC = AA13 IOSTANDARD = HSTL_I;
NET qdriip_sa[14] LOC = AC13 IOSTANDARD = HSTL_I;
NET qdriip_sa[15] LOC = Y13 IOSTANDARD = HSTL_I;
NET qdriip_sa[16] LOC = AA12 IOSTANDARD = HSTL_I;
NET qdriip_sa[17] LOC = AA10 IOSTANDARD = HSTL_I;
NET qdriip_sa[18] LOC = AB9 IOSTANDARD = HSTL_I;
NET qdriip_w_n LOC = AD9 IOSTANDARD = HSTL_I;
NET qdriip_r_n LOC = AE7 IOSTANDARD = HSTL_I;
NET qdriip_dll_off_n LOC = AC7 IOSTANDARD = HSTL_I;
NET qdriip_bw_n[0] LOC = W11 IOSTANDARD = HSTL_I;
NET qdriip_bw_n[1] LOC = V11 IOSTANDARD = HSTL_I;
NET qdriip_cq_p[0] LOC = AB16 IOSTANDARD = HSTL_I_DCI;
NET qdriip_cq_n[0] LOC = AC18 IOSTANDARD = HSTL_I_DCI;
NET qdriip_qvld[0] LOC = AA19 IOSTANDARD = HSTL_I_DCI;
NET qdriip_k_p[0] LOC = AE12 IOSTANDARD = DIFF_HSTL_I;
NET qdriip_k_n[0] LOC = AF12 IOSTANDARD = DIFF_HSTL_I;
Back to Top

BPI Flash

Port Name IO Location IO Standard Type
NET bpi_clk_out LOC = C8 IOSTANDARD = LVCMOS33;
NET bpi_we_n LOC = L18 IOSTANDARD = LVCMOS33;
NET bpi_oe_n LOC = M17 IOSTANDARD = LVCMOS33;
NET bpi_ce_n LOC = C23 IOSTANDARD = LVCMOS33;
NET bpi_adv LOC = D20 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[0] LOC = J23 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[1] LOC = K23 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[2] LOC = K22 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[3] LOC = L22 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[4] LOC = J25 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[5] LOC = J24 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[6] LOC = H22 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[7] LOC = H24 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[8] LOC = H23 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[9] LOC = G21 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[10] LOC = H21 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[11] LOC = H26 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[12] LOC = J26 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[13] LOC = E26 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[14] LOC = F25 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[15] LOC = G26 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[16] LOC = K17 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[17] LOC = K16 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[18] LOC = L20 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[19] LOC = J19 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[20] LOC = J18 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[21] LOC = J20 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[22] LOC = K20 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[23] LOC = G20 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[24] LOC = H19 IOSTANDARD = LVCMOS33;
NET bpi_addr_cmd[25] LOC = E20 IOSTANDARD = LVCMOS33;
NET bpi_data[0] LOC = B24 IOSTANDARD = LVCMOS33;
NET bpi_data[1] LOC = A25 IOSTANDARD = LVCMOS33;
NET bpi_data[2] LOC = B22 IOSTANDARD = LVCMOS33;
NET bpi_data[3] LOC = A22 IOSTANDARD = LVCMOS33;
NET bpi_data[4] LOC = A23 IOSTANDARD = LVCMOS33;
NET bpi_data[5] LOC = A24 IOSTANDARD = LVCMOS33;
NET bpi_data[6] LOC = D26 IOSTANDARD = LVCMOS33;
NET bpi_data[7] LOC = C26 IOSTANDARD = LVCMOS33;
NET bpi_data[8] LOC = C24 IOSTANDARD = LVCMOS33;
NET bpi_data[9] LOC = D21 IOSTANDARD = LVCMOS33;
NET bpi_data[10] LOC = C22 IOSTANDARD = LVCMOS33;
NET bpi_data[11] LOC = B20 IOSTANDARD = LVCMOS33;
NET bpi_data[12] LOC = A20 IOSTANDARD = LVCMOS33;
NET bpi_data[13] LOC = E22 IOSTANDARD = LVCMOS33;
NET bpi_data[14] LOC = C21 IOSTANDARD = LVCMOS33;
NET bpi_data[15] LOC = B21 IOSTANDARD = LVCMOS33;
Back to Top

SD Card Connector

Port Name IO Location IO Standard Type
NET sd-cd LOC = AE15 IOSTANDARD = LVCMOS18 | PULLUP;
NET sd-wp LOC = AF15 IOSTANDARD = LVCMOS18 | PULLUP;
NET sd-cclk LOC = AA18 IOSTANDARD = LVCMOS18;
NET sd-cmd LOC = AF18 IOSTANDARD = LVCMOS18;
NET sd-d0 LOC = AE17 IOSTANDARD = LVCMOS18;
NET sd-d1 LOC = AF17 IOSTANDARD = LVCMOS18;
NET sd-d2 LOC = AD15 IOSTANDARD = LVCMOS18;
NET sd-d3 LOC = AE18 IOSTANDARD = LVCMOS18;
Back to Top

PCI Express

PCIe Lane Transceiver Placement
Lane 0 GTXE2_CHANNEL_X0Y3
Lane 1 GTXE2_CHANNEL_X0Y2
Lane 2 GTXE2_CHANNEL_X0Y1
Lane 3 GTXE2_CHANNEL_X0Y0
Port Name IO Location IO Standard Type
NET pcie-tx0_p LOC = H2;
NET pcie-rx0_p LOC = J4;
NET pcie-tx0_n LOC = H1;
NET pcie-rx0_n LOC = J3;
NET pcie-tx1_p LOC = K2;
NET pcie-rx1_p LOC = L4;
NET pcie-tx1_n LOC = K1;
NET pcie-rx1_n LOC = L3;
NET pcie-tx2_p LOC = M2;
NET pcie-rx2_p LOC = N4;
NET pcie-tx2_n LOC = M1;
NET pcie-rx2_n LOC = N3;
NET pcie-tx3_p LOC = P2;
NET pcie-rx3_p LOC = R4;
NET pcie-tx3_n LOC = P1;
NET pcie-rx3_n LOC = R3;
NET pcie-clk_p LOC = H6;
NET pcie-clk_n LOC = H5;
NET pcie-perstn LOC = L17 IOSTANDARD = LVCMOS33 | PULLUP | NODELAY;
NET pcie-wake LOC = K18 IOSTANDARD = LVCMOS33;
NET pcie-prsnt LOC = AA7 IOSTANDARD = LVCMOS18;
Back to Top

Ethernet PHYS

Port Name IO Location IO Standard Type
NET mdc LOC = V13 IOSTANDARD = LVCMOS18;
NET mdio LOC = W13 IOSTANDARD = LVCMOS18;
NET phy_rstn_1 LOC = D18 IOSTANDARD = LVCMOS33;
NET phy_rstn_2 LOC = E25 IOSTANDARD = LVCMOS33;
NET phy_rstn_3 LOC = K21 IOSTANDARD = LVCMOS33;
NET phy_rstn_4 LOC = L23 IOSTANDARD = LVCMOS33;
NET phy_intrn_1 LOC = J8 IOSTANDARD = LVCMOS18 | PULLUP;
NET phy_intrn_2 LOC = J14 IOSTANDARD = LVCMOS18 | PULLUP;
NET phy_intrn_3 LOC = K15 IOSTANDARD = LVCMOS33 | PULLUP;
NET phy_intrn_4 LOC = M16 IOSTANDARD = LVCMOS33 | PULLUP;
NET rgmii_rxd_1[0] LOC = B11 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_1[1] LOC = A10 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_1[2] LOC = B10 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_1[3] LOC = A9 IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[0] LOC = A8 IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[1] LOC = D8 IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[2] LOC = G9 IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[3] LOC = H9 IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_1 LOC = B12 IOSTANDARD = LVCMOS18;
NET rgmii_rxc_1 LOC = E10 IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_1 LOC = H8 IOSTANDARD = LVCMOS18;
NET rgmii_txc_1 LOC = B9 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[0] LOC = A13 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[1] LOC = C9 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[2] LOC = D11 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[3] LOC = C11 IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[0] LOC = D10 IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[1] LOC = G10 IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[2] LOC = D9 IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[3] LOC = F9 IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_2 LOC = A12 IOSTANDARD = LVCMOS18;
NET rgmii_rxc_2 LOC = C12 IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_2 LOC = F8 IOSTANDARD = LVCMOS18;
NET rgmii_txc_2 LOC = J10 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[0] LOC = A14 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[1] LOC = B14 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[2] LOC = E12 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[3] LOC = D13 IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[0] LOC = G12 IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[1] LOC = F13 IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[2] LOC = F12 IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[3] LOC = H11 IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_3 LOC = C13 IOSTANDARD = LVCMOS18;
NET rgmii_rxc_3 LOC = E11 IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_3 LOC = F10 IOSTANDARD = LVCMOS18;
NET rgmii_txc_3 LOC = E13 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[0] LOC = B15 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[1] LOC = F14 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[2] LOC = C14 IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[3] LOC = H12 IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[0] LOC = J13 IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[1] LOC = G14 IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[2] LOC = H14 IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[3] LOC = H13 IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_4 LOC = A15 IOSTANDARD = LVCMOS18;
NET rgmii_rxc_4 LOC = G11 IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_4 LOC = J11 IOSTANDARD = LVCMOS18;
NET rgmii_txc_4 LOC = D14 IOSTANDARD = LVCMOS18;
Back to Top

PIC Interface

Port Name IO Location IO Standard Type
NET pic2fpga_sck LOC = AA17 IOSTANDARD = LVCMOS18;
NET pic2fpga_sdo LOC = V16 IOSTANDARD = LVCMOS18;
NET pic2fpga_ss_n LOC = W16 IOSTANDARD = LVCMOS18;
NET pic2fpga_gpi00 LOC = W18 IOSTANDARD = LVCMOS18;
NET pic2fpga_gpi01 LOC = V17 IOSTANDARD = LVCMOS18;
NET pic2fpga_sdi LOC = W15 IOSTANDARD = LVCMOS18;
NET fpga2pic_sck LOC = W14 IOSTANDARD = LVCMOS18;
NET fpga2pic_sdi LOC = V14 IOSTANDARD = LVCMOS18;
NET fpga2pic_ss_n LOC = V18 IOSTANDARD = LVCMOS18;
NET fpga2pic_sdo LOC = V19 IOSTANDARD = LVCMOS18;
Back to Top

On-Board LED and Button I/O

Port Name IO Location IO Standard Type
NET led_0 LOC = E17 IOSTANDARD = LVCMOS33;
NET led_1 LOC = AF14 IOSTANDARD = LVCMOS18;
NET led_2 LOC = F17 IOSTANDARD = LVCMOS33;
NET led_3 LOC = W19 IOSTANDARD = LVCMOS18;
NET btn_0 LOC = W6 IOSTANDARD = LVCMOS15;
NET btn_1 LOC = E18 IOSTANDARD = LVCMOS33;
NET btn_2 LOC = AC6 IOSTANDARD = LVCMOS15;
NET btn_3 LOC = AB6 IOSTANDARD = LVCMOS15;
Back to Top

PMOD Connectors

Port Name IO Location IO Standard Type
NET pmod_ja_1 LOC = D19 IOSTANDARD = LVCMOS33;
NET pmod_ja_2 LOC = E23 IOSTANDARD = LVCMOS33;
NET pmod_ja_3 LOC = D25 IOSTANDARD = LVCMOS33;
NET pmod_ja_4 LOC = F23 IOSTANDARD = LVCMOS33;
NET pmod_ja_7 LOC = F19 IOSTANDARD = LVCMOS33;
NET pmod_ja_8 LOC = G22 IOSTANDARD = LVCMOS33;
NET pmod_ja_9 LOC = D24 IOSTANDARD = LVCMOS33;
NET pmod_ja_10 LOC = E21 IOSTANDARD = LVCMOS33;
NET pmod_jb_1 LOC = F20 IOSTANDARD = LVCMOS33;
NET pmod_jb_2 LOC = E15 IOSTANDARD = LVCMOS33;
NET pmod_jb_3 LOC = H18 IOSTANDARD = LVCMOS33;
NET pmod_jb_4 LOC = G19 IOSTANDARD = LVCMOS33;
NET pmod_jb_7 LOC = H17 IOSTANDARD = LVCMOS33;
NET pmod_jb_8 LOC = J21 IOSTANDARD = LVCMOS33;
NET pmod_jb_9 LOC = L19 IOSTANDARD = LVCMOS33;
NET pmod_jb_10 LOC = F18 IOSTANDARD = LVCMOS33;
Back to Top

FMC Connector

IOSTANDARD depends upon VADJ for LA, HA and CLK pins.

Port Name IO Location IO Standard Type
NET VADJ_EN LOC = AD16 IOSTANDARD = LVCMOS18;
NET SET_VADJ1 LOC = AF19 IOSTANDARD = LVCMOS18;
NET SET_VADJ2 LOC = AF20 IOSTANDARD = LVCMOS18;
NET FMC_LA00_P LOC = Y22;
NET FMC_LA00_N LOC = AA22;
NET FMC_LA01_P LOC = N21;
NET FMC_LA01_N LOC = N22;
NET FMC_LA02_P LOC = AB22;
NET FMC_LA02_N LOC = AC22;
NET FMC_LA03_P LOC = AF24;
NET FMC_LA03_N LOC = AF25;
NET FMC_LA04_P LOC = AA25;
NET FMC_LA04_N LOC = AB25;
NET FMC_LA05_P LOC = AE23;
NET FMC_LA05_N LOC = AF23;
NET FMC_LA06_P LOC = W20;
NET FMC_LA06_N LOC = Y21;
NET FMC_LA07_P LOC = AB26;
NET FMC_LA07_N LOC = AC26;
NET FMC_LA08_P LOC = AD26;
NET FMC_LA08_N LOC = AE26;
NET FMC_LA09_P LOC = Y25;
NET FMC_LA09_N LOC = Y26;
NET FMC_LA10_P LOC = V21;
NET FMC_LA10_N LOC = W21;
NET FMC_LA11_P LOC = W25;
NET FMC_LA11_N LOC = W26;
NET FMC_LA12_P LOC = W23;
NET FMC_LA12_N LOC = W24;
NET FMC_LA13_P LOC = U22;
NET FMC_LA13_N LOC = V22;
NET FMC_LA14_P LOC = R26;
NET FMC_LA14_N LOC = P26;
NET FMC_LA15_P LOC = T24;
NET FMC_LA15_N LOC = T25;
NET FMC_LA16_P LOC = V23;
NET FMC_LA16_N LOC = V24;
NET FMC_LA17_P LOC = R22;
NET FMC_LA17_N LOC = R23;
NET FMC_LA18_P LOC = P23;
NET FMC_LA18_N LOC = N23;
NET FMC_LA19_P LOC = T22;
NET FMC_LA19_N LOC = T23;
NET FMC_LA20_P LOC = R25;
NET FMC_LA20_N LOC = P25;
NET FMC_LA21_P LOC = M24;
NET FMC_LA21_N LOC = L24;
NET FMC_LA22_P LOC = M25;
NET FMC_LA22_N LOC = L25;
NET FMC_LA23_P LOC = P24;
NET FMC_LA23_N LOC = N24;
NET FMC_LA24_P LOC = U17;
NET FMC_LA24_N LOC = T17;
NET FMC_LA25_P LOC = T18;
NET FMC_LA25_N LOC = T19;
NET FMC_LA26_P LOC = M21;
NET FMC_LA26_N LOC = M22;
NET FMC_LA27_P LOC = N26;
NET FMC_LA27_N LOC = M26;
NET FMC_LA28_P LOC = R16;
NET FMC_LA28_N LOC = R17;
NET FMC_LA29_P LOC = K25;
NET FMC_LA29_N LOC = K26;
NET FMC_LA30_P LOC = N19;
NET FMC_LA30_N LOC = M20;
NET FMC_LA31_P LOC = P19;
NET FMC_LA31_N LOC = P20;
NET FMC_LA32_P LOC = P16;
NET FMC_LA32_N LOC = N17;
NET FMC_LA33_P LOC = N18;
NET FMC_LA33_N LOC = M19;
NET FMC_HA00_P LOC = U19;
NET FMC_HA00_N LOC = U20;
NET FMC_HA01_P LOC = T20;
NET FMC_HA01_N LOC = R20;
NET FMC_HA02_P LOC = AD23;
NET FMC_HA02_N LOC = AD24;
NET FMC_HA03_P LOC = AB21;
NET FMC_HA03_N LOC = AC21;
NET FMC_HA04_P LOC = U24;
NET FMC_HA04_N LOC = U25;
NET FMC_HA05_P LOC = U26;
NET FMC_HA05_N LOC = V26;
NET FMC_HA06_P LOC = AD25;
NET FMC_HA06_N LOC = AE25;
NET FMC_HA07_P LOC = AD21;
NET FMC_HA07_N LOC = AE21;
NET FMC_HA08_P LOC = AE22;
NET FMC_HA08_N LOC = AF22;
NET FMC_HA09_P LOC = R18;
NET FMC_HA09_N LOC = P18;
NET FMC_HA10_P LOC = U16;
NET FMC_HA10_N LOC = N16;
NET FMC_HA11_P LOC = Y20;
NET FMC_HA11_N LOC = U21;
NET FMC_CLK0_M2C_N LOC = P21;
NET FMC_CLK0_M2C_P LOC = R21;
NET FMC_CLK1_M2C_N LOC = AC24;
NET FMC_CLK1_M2C_P LOC = AC23;
NET FMC_CLK2_M2C_N LOC = AB24;
NET FMC_CLK2_M2C_P LOC = AA23;
NET FMC_CLK3_M2C_N LOC = AA24;
NET FMC_CLK3_M2C_P LOC = Y23;
NET FMC_DP0_M2C_N LOC = C3;
NET FMC_DP0_M2C_P LOC = C4;
NET FMC_DP0_C2M_N LOC = B1;
NET FMC_DP0_C2M_P LOC = B2;
NET FMC_DP1_M2C_N LOC = E3;
NET FMC_DP1_M2C_P LOC = E4;
NET FMC_DP1_C2M_N LOC = D1;
NET FMC_DP1_C2M_P LOC = D2
NET FMC_DP2_M2C_N LOC = B5;
NET FMC_DP2_M2C_P LOC = B6;
NET FMC_DP2_C2M_N LOC = A3;
NET FMC_DP2_C2M_P LOC = A4;
NET FMC_DP3_M2C_N LOC = G3;
NET FMC_DP3_M2C_P LOC = G4;
NET FMC_DP3_C2M_N LOC = F1;
NET FMC_DP3_C2M_P LOC = F2;
NET FMC_GBTCLK0_M2C_N LOC = F5;
NET FMC_GBTCLK0_M2C_P LOC = F6;
NET FMC_GBTCLK1_M2C_N LOC = D5;
NET FMC_GBTCLK1_M2C_P LOC = D6;
Back to Top
Add a custom footer
⚠️ **GitHub.com Fallback** ⚠️