AXI4 Lite and Register Bus Bridge - NetFPGA/NetFPGA-public GitHub Wiki

Name

nf10_axilite_rbs_bridge

Version

v1.00a

Author

Gianni Anitchi (gianni.antichi_at_iet.unipi.it)

Muhammad Shahbaz (muhammad.shahbaz_at_cl.cam.ac.uk)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/contrib/pcores/nf10_axilite_rbs_bridge_v1_00_a/

Interface Types

AXI4-Lite

Register-Stream

Busses

S_AXI: Slave AXI4-Lite

M_RBS: Master Register-Stream

S_RBS: Slave Register-Stream

Parameters

C_S_AXI_DATA_WIDTH: Data width of the slave AXI4-Lite bus.

C_S_AXI_ADDR_WIDTH: Address width of the slave AXI4-Lite bus.

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

C_RBS_SRC_WIDTH: Source width of the Register-Stream bus.

C_RBS_RING_SIZE: Ring size of the Register-Stream bus. Ring size is the number of modules in the NetFPGA-1G register pipeline.

C_RBS_SRC_ID: Source ID of the Register-Stream bus.

Register map

No registers are implemented for v1.00a.

Description

This block functions as a bridge between the AXI lite bus and the native NetFPGA-1G Register stream bus. It enables existing NetFPGA-1G modules to be integrated in the new 10G platform with minimal changes.

Instructions

  1. This block provides a contiguous memory space for the entire NetFPGA-1G register pipeline. For now, internal mapping for each module within the pipeline is hard-coded by the user. A unified register system, currently under development, will later on automate this process.

  2. Add the following TIG constraints in the UCF to tell the tool to ignore timing constraints on all signals crossing between the control and core clock domain. The axi_interconnect handles these signals by adding necessary synchronization logic.

TIMESPEC "TS_TIG_0" = FROM "CORE_CLK" TO "CTRL_CLK" TIG; 
TIMESPEC "TS_TIG_1" = FROM "CTRL_CLK" TO "CORE_CLK" TIG;