RIFFA DMA Engine - NetFPGA/NetFPGA-SUME-public GitHub Wiki
Name
nf_riffa_dma
Version
v1.00
Author
Yury Audzevich
Type
IP core (HW)
Location
lib/hw/std/cores/nf_riffa_dma_v1_0_0
Interface Types
AXI4-Stream
AXI-Lite
Busses
M_AXIS_CQ: Master AXI4-Stream bus, 128b - Completer reQuest
M_AXIS_RC: Master AXI4-Stream bus, 128b - Requester Completion
M_AXIS_XGE_TX: Master AXI4-Stream bus, 256b - Tx Data (From the host to the network)
S_AXIS_XGE_RX: Slave AXI4-Stream bus, 256b - Rx Data (From the network to the host)
S_AXIS_CC: Slave AXI4-Stream bus, 128b - Completer Completion
S_AXIS_RQ: Slave AXI4-Stream bus, 128b - Requester reQuest
M_AXI: Master AXI4-Lite
Parameters
TBD
Register map
TBD
Description
The RIFFA DMA Module is based on the DMA created by the RIFFA project (but is not identical). The module supports PCI Express Gen.2 x8 as well as packet transactions. It receives incoming transactions (both packets and registers access) from the PCIe IP and converts them to AXI-Stream transactions towards the data path (for packets) and AXI-Lite transactions toward the AXI Interconnect (for registers access). The Module supports the buffer handling required for DMA transactions and has a dedicated driver. Only a single channel and a single BAR is supported by this design.