Contrib. Core: Input Arbiter 6in - NetFPGA/NetFPGA-SUME-public GitHub Wiki

Name

input_arbiter_6in

Version

v1.0.0

Author

Pietro Bressana

Type

Contrib IP core (HW)

Location

lib/hw/contrib/cores/input_arbiter_6in_v1_0_0/

Interface Types

AXI4-Stream

AXI-Lite

Busses

M_AXIS: Master AXI4-Stream bus, Variable width

S_AXIS_0: Slave AXI4-Stream bus, Variable width

S_AXIS_1: Slave AXI4-Stream bus, Variable width

S_AXIS_2: Slave AXI4-Stream bus, Variable width

S_AXIS_3: Slave AXI4-Stream bus, Variable width

S_AXIS_4: Slave AXI4-Stream bus, Variable width

S_AXIS_5: Slave AXI4-Stream bus, Variable width

S_AXI: Slave AXI4-Lite

Parameters

C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus.

C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.

C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus.

C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus 0~4.

C_S_AXIS6_TUSER_WIDTH: Data width of the slave TUSER bus 5.

Register map

0x0 : ID - Block ID

0x4 : VERSION - Block Version

0x8 : FLIP - Returns the negative value of a written register

0xC : PKTIN - Total number of incoming packets

0x10 : PKTOUT - Total number of outgoing packets

0x14 : DEBUG - Debug register, returns the written value plus a preconfigured value

Description

This version of the Input Arbiter provides support for an additional internal high-priority 50Gbps queue, while running round-robin arbitration on the external interfaces. Metadata bus is extended to 256b.