UE14500 Processor

The UE14500 is named after the Motorola MC14500 1-bit ICU. The MC14500 was primarily intended for industrial applications and to replace old relay ladder logic state machine systems. However, the architecture was strikingly similar to some other processors of the time period, albeit greatly pared down. As such, I felt it was an excellent candidate for the vacuum tube processor. However, there have been some changes to the architecture, most notably, we have upgraded the Logic Unit to a full-fledged Arithmetic Logic Unit.

Architecture

The UE14500 uses a 1-bit data bus and a 4-bit instruction for 16 OpCodes. The basic architecture is centered around the idea of data being stored in an accumulating Result Register (RR). The Arithmetic Logic Unit (ALU) will perform operations using the value stored in RR and the value currently asserted to the Data Bus. It will then store the result of the operation back into RR.

Additionally, input into the processor can be gated through the Input Enable Register (IEN). During an STO or STOC operation, the processor will assert to the data bus as well as assert the Write pin. The Write pin can be gated through the Output Enable Register (OEN). Through the use of IEN and OEN, input and output can be effectively gated based upon conditional input, allowing instructions to be skipped.

Here is an architecture diagram for the UE14500 processor.

Instructions

The instruction set has been modified from the MC14500 to reflect the new ALU operations as well as some minor changes for future Input and Output control. The processor is a true RISC design, executing one instruction per clock cycle.

Hex	Binary	OpCode	Operation
0	0000	NOP0	No change in registers. RR -> RR, FLG0 ^
1	0001	LD	Load Result Register. Data -> RR
2	0010	ADD	Add RR and Data. Data + RR -> RR
3	0011	SUB	Subtract RR and Data. Data - RR -> RR
4	0100	ONE	Force One into RR. 1 -> RR, 0 -> CAR
5	0101	NAND	NAND Data and RR. Q(RR・Data) -> RR
6	0110	OR	OR Data and RR. RR or Data -> RR
7	0111	XOR	XOR Data and RR. If RR != Data, 1 -> RR
8	1000	STO	Store. RR -> Data, WRT ^
9	1001	STOC	Store complement. QRR -> Data, WRT ^
A	1010	IEN	Input Enable Register. Data -> IEN
B	1011	OEN	Output Enable Register. Data -> OEN
C	1100	IOC	Input Output Control. IOC ^
D	1101	RTN	Return from subroutine. RTN ^, Skip next instruction
E	1110	SKZ	Skip if Zero. IF RR = 0, Skip next instruction
F	1111	NOPF	No change in registers. RR -> RR, FLGF ^

Processor Logic

The entire processor was first simulated in Logisim. The Logisim logic gate level version of the processor then became the blueprint for the actual build itself.

The Logisim file itself is available for download by clicking this link.

Below is an image of the above Logisim file.

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PCB Layout

The entire PCBs were designed using DesignSparkPCB and trying to adhered to a maximum board size of 150mm x 100mm as that was the size of the single sided PCBs that were purchased for this build. The benefit of using multiple, smaller boards is that the build could be changed or updated during various stages. The downside is additional complexity as well as an imperfect solution for the connectors between boards.

Here is a view of the entire PCB layout for the Processor.

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