Registers

The instruction, IEN, OEN, and SKZ registers all use the exact same design. However, the Result Register and Carry Register required a more robust design in order for the processor to operate correctly. This section will outline the two different register designs that are used in the processor.

Instruction, IEN, OEN and SKZ Design

A standard edge triggered D Flip Flop built from NOR gates is used for the Instruction, IEN, OEN and SKZ register designs. These registers change state on the rising edge. However, a unique clock signal is used to enure that the Instruction Register latches before any other registers latch. This is the logic diagram for the flip flop. For more information on how to build the logic gates using low voltage vacuum tubes, see the logic gates page.

Result Register and Carry Register Design

A more robust master/slave or primary/secondary D Flip Flop is used for the RR and Carry registers. This was chosen to prevent racing conditions due to the input changing faster than the Flip Flop would be capable of switching. By adopting this design, the value is locked in and the Flip Flop switches very stably, even if the result of the flip flop directly impacts the input data value. Furthermore, the RR and Carry registers change state on the clock falling edge. For more information on how to build the logic gates using low voltage vacuum tubes, see the logic gates page.