MC14500

The Motorola MC14500 is a 1-bit Industrial Control Unit specifically designed to replace old relay ladder logic systems. However, it has an accumulating Results Register, a Logic Unit, and other gubbins that make it frighteningly close to a full-on 1-bit microprocessor. It is designed in such a way that the processor can be used in any variety of system configurations by moving memory and program control off chip.

(Image source)

Architecture

The UMC14500 uses a 1-bit data bus and a 4-bit instruction for 16 OpCodes. The basic architecture is centered around the idea of data being stored in an accumulating Result Register (RR). The Logic Unit (LU) will perform operations using the value stored in RR and the value currently asserted to the Data Bus. It will then store the result of the operation back into RR.

Additionally, input into the processor can be gated through the Input Enable Register (IEN). During an STO or STOC operation, the processor will assert to the data bus as well as assert the Write pin. The Write pin can be gated through the Output Enable Register (OEN). Through the use of IEN and OEN, input and output can be effectively gated based upon conditional input, allowing instructions to be skipped.

Here is an architecture diagram for the UE14500 processor.

Instruction Set

This is the Instruction Set of the MC14500.

Hex	Binary	OpCode	Operation
0	0000	NOP0	No change in registers. RR -> RR, FLG0 ^
1	0001	LD	Load Result Register. Data -> RR
2	0010	LDC	Load Complement. QData -> RR
3	0011	AND	AND Data and RR. RR・Data -> RR
4	0100	ANDC	AND Complement Data and RR. RR・QData -> RR
5	0101	OR	OR Data and RR. RR or Data -> RR
6	0110	ORC	OR Complement Data and RR. RR + QData -> RR
7	0111	XNOR	XNOR Data and RR. If RR = Data, 1 -> RR
8	1000	STO	Store. RR -> Data, WRT ^
9	1001	STOC	Store complement. QRR -> Data, WRT ^
A	1010	IEN	Input Enable Register. Data -> IEN
B	1011	OEN	Output Enable Register. Data -> OEN
C	1100	JMP	Jump. JMP Flag ^
D	1101	RTN	Return from subroutine. RTN Flag ^, Skip next instruction
E	1110	SKZ	Skip if Zero. IF RR = 0, Skip next instruction
F	1111	NOPF	No change in registers. RR -> RR, FLGF ^

Minimal ICU System

The ICU handbook outlines an absolute minimal ICU system. It features just an 8-bit instruction word (4-bit instruction, 1-bit chip select, 3-bit memory address), three I/O registers, and a program clock that can be any length the user desires (though JMP and JSR are not fully implemented in this system).

I once built this exact system up on a breadboard and it was a ton of fun. There is a full playlist available on Youtube here.

Reverse Engineering

In the course of developing the tube computer, I hit a point where it would have been beneficial to know a little more about how Motorola designed the chip internally. Well, there's really only one way to know for sure and that is to decap the chip. The chip went off to John McMaster who did an amazing job decapping the IC, and then removing the metal layer to get a look at the silicon underneath. From here, the images went to the insanely talented Ken Shirriff who walked me through reverse engineering the chip.

Check out Ken's amazing article on the MC14500 here!

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Logic Gate Version

Initially, the plan was to replicate the MC14500 in vacuum tubes faithfully, and this logic diagram was the result. However, midway through the design, we decided to increase the capability of the system by upgrading from a Logic Unit to a full Arithmetic Logic Unit, resulting in what we now dub the UE14500 Processor.