Clocking Concept

The UE14500 is a fairly extreme RISC design with just 16 instructions and one instruction execution per clock cycle. Due to the nature of tubes and their comparatively slow/linear turn on rates, as well as the inconsistency from using second hand tubes, there were initially many timing problems. The instruction register would sometimes latch instructions in at different rates which would cause spurious or inconsistent reactions in other registers or in the ALU, resulting in incorrect values being used or stored. The solution was to create two clock signals, one delayed slightly behind the other.

Additionally, the register design being used for the Instruction, IEN, OEN and SKZ registers requires an inverted clock. The IEN and OEN registers are using a NAND gate on the clock input signal to both gate the input and invert the timing signal. The Instruction Register however, does not have any inverters included, and therefore the incoming clock signal for the Instruction Register (CL1 in the image below) must be inverted at the clock itself.

Schematic

CL1 is used for the Instruction Register and must be inverted. Additionally, the output signal must cleanly drive all four inputs to the Instruction Register, necessitating the use of a cathode follower to buffer the clock signal. However, since the filaments for the tubes are being run in series and powered off the +24V rail or the -12V rail, there had to be an even number of tubes, notably four or six. Also, because I don't do any math, I was unsure how many buffers would be necessary. In reality, only a single buffer would have been plenty, but I went for the overkill option.

CL2 is used for all remaining registers and functions of the processor. Any function that uses the signal already has an inverter included if necessary, which means this signal did not need to be inverted. However, it had to be delayed a certain amount of time beyond CL1. There were many more complicated methods considered, but just adding a simple RC circuit to the input was the simplest solution. On the actual computer, the capacitor can be hot swapped and the resistor is a linear potentiometer, allowing for supreme adjustment in just how the long the delay can be.

Clock Waveform

Here is a shot of the waveform from the actual circuit. The second waveform is offset further down to help it be easier to see. The waveforms are nice, crisp square waves and the amount of delay is clearly visible here. In practice, the delay was very, very adjustable, which should allow the system to be fine tuned to the best clock speed.

And here is the clock, on the board during initial testing.