Arithmetic Logic Unit

The Motorola MC14500 that the processor is based on uses just a Logic Unit, only capable of doing boolean logic operations. In order to do something like a full add of two operands with a carry, it takes approximately 12 instructions. Doing full arithmetic wasn't exactly something that was necessary for the intended applications of the chip, so a full adder to do arithmetic wasn't included. For the UE14500, we're aiming for a more general computing type application, so having a more fully featured ALU was important.

Operations

Since the UE14500 was based heavily on the MC14500, we were still using a 4-bit instruction, which meant we only had a total of 7-instructions available for the ALU. After some heavy redesign work, we came up with the following ALU operations:

MC14500 on left, new UE14500 ALU on right.

MC14500	Operation	_	UE14500	Operation
0001	LD - Load	_	0001	LD - Load
0010	LDC - Load Complement	_	0010	ADD - Addition
0011	AND - Logical AND	_	0011	SUB - Subtraction
0100	ANDC - Logical AND Compliment	_	0100	ONE - Force one into RR
0101	OR - Logical OR	_	0101	NAND - Logical NAND
0110	ORC - Logical OR Compliment	_	0110	OR - Logical OR
0111	XNOR - Logical Exclusive NOR	_	0111	XOR - Logical Exclusive OR

Design

Here is the full logic gate design that is being used in the UE14500 currently. This was all designed in Logisim and the file is available by clicking this link. It should be noted that this is not the most optimal design. Much of this was designed around the specific construction restraints inherent to the UE14500, which sometimes means excess gates are used in places that would otherwise not make sense. Also, I'm 100% confident there's a more efficient way to design this (see below).

An Alternate Design

Serayen on the Discord chat server has slowly been designing a discrete version of the UE14500 and found several optimizations that could be made to bring the total transistor count down. Check out the full Logisim design at this link. Below is the ALU from Serayen's design. It should be noted that I did pull all the individual logic gate level designs and squeezed them into a single design for this image. As such, there may be errors in this introduced by me. Also, this particular design will require changes to the instruction decoder. Refer to the Logisim file linked here again for proper detail.