Registers

There are eight registers available, though care should be taken with some registers, particularly the X, S, C and P registers, as these are used for specific functions during some OpCodes.

Name	Byte	Full Word	High Byte	Low Byte	Usage	Notes
A	01	A	AU	AL	Primary Accumulator	Primary register, commonly used in implicit operations, can use full addressing modes
B	23	B	BU	BL	Secondary Accumulator	Primary register, commonly used in implicit operations, can use full addressing modes
X	45	X			Primary Index	Can only do word operations (Not true for CPU6?)
Y	67	Y	YU	YL	Secondary Index or Working Register	Index registers or working storage registers
Z	89	Z	ZU	ZL	Secondary Index or Working Register	Index registers or working storage registers
S	AB	S	SU	SL	Stack Register	Global among all interrupt levels and used to maintain stack during subroutine exits and entries
C	CD	C			Context Register	Contains the status condition indicators (fault, link, minus, and value) and preceding interrupt level
P	EF	P			Program Counter Base	Contains initial program counter value to be used when starting up or returning from interrupt

Contexts

Each register and the flags appears to exist in 16 contexts and these contexts are mapped between 0x0000 and 0x00FF 16 bytes per context starting with context 0 and working upwards. The registers are stored in the memory in the order given above. Writing to the memory of another context updates the registers for that context. Writing to the memory for your own context appears to change the register value except for P and C.

The processor starts in context 0. Context 15 is used by what appears to be a syscall instruction, context 6 is used by the MUX interrupt test, context 1 is used programmatically during MMU testing.

Interrupts (or at least the one sample we have) are processed by a hardware triggered context switch, the execution of code in the new context, and then an 0x0A instruction.

Context Register

The context register holds the previous IPL, the condition codes and the Page Table Map register.

The register organisation is as follows

Bit(s)	Function
15-12	Previous IPL
11-8	Unknown, not used?
7	Value (Zero)
6	Minus (Sign)
5	Fault (Overflow)
4	Link (Carry)
3-0	Page Table Map for context