OpC_20 2F - Nakazoto/CenturionComputer GitHub Wiki

OpCodes 0x20 ~ 0x2F

0x20: INRB

Increment byte

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0x21: DCRB

Decrement byte

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0x22: CLRB

Clear byte

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0x23: IVRB

Invert byte

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0x24: SRRB

Arithmetic shift byte right

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0x25: SLRB

Arithmetic shift byte left

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0x26: RRRB

Rotate byte right (wraps through carry)

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0x27: RLRB

Rotate byte left (wraps through carry)

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0x28: INAB

Increment A register byte

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0x29: DCAB

Decrement A register byte

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0x2A: CLAB

Clear A register byte

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0x2B: IVAB

Invert A register byte

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0x2C: SRAB

Shift A register byte right

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0x2D: SLAB

Shift A register byte left

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0x2E: PageTable

These instructions are of the form 2E ssssmmnn where ssss is the instruction selector and mm is the addressing mode of the first operand and nn is the addressing mode of the second operand.

Addressing modes

This section describes the addressing modes for the 2e instruction. This is very much WIP. These modes are shared with other instructions.

For mode 2, the microcode indicates whether the register will be in the high nibble or low nibble of the relevant byte.

Mode Function Description
0 EA <- (PC) Direct
1 EA <- imm8/imm16 + r1 + r2 (if r2 is not AW) r1/r2 are 16 bit registers indicated in byte following instruction high and low nibble respectively. imm8/imm16 follows r1/r2. Imm16 is used if r1 is odd (the word register is still used as the index)
2 EA <- R, R in high or low nibble of byte at PC determined by microcode Register
3 EA <- PC Literal (illegal when address must be specified). Size provided in microcode.

Selector

Selector Opcode Operand 1 Operand 2 Description
0 WPF Low 3 bits: page table map. High 5 bits: count Address Write Page File - write count page table entries with page table map from Operand 2 address
1 RPF Low 3 bits: page table map. High 5 bits: count Address Read Page File - read count page table entries with page table map to Operand 2 address. Set top bit from MSR
2 WPF1 Low 3 bits: page table map. High 5 bits: Page table index Address Write Page File 1 entry from Operand 2 address
3 RPF1 Low 3 bits: page table map. High 5 bits: Page table index Address Read Page File 1 entry to Operand 2 address. Set top bit from MSR
4 WPFH Low 3 bits: page table map. High 5 bits: Page table index Address Write Page File High. Writes 32-index entries from Operand 2 address
5 RPFH Low 3 bits: page table map. High 5 bits: Page table index Address Read Page File High. Reads 32-index entries to Operand 2 address. Set top bit from MSR

0x2F: DMA (Direct Memory Access)

These instructions are mainly concerning DMA. There are ten DMA instructions. The instructions are of the form 2e rs where r is a register and s is the instruction selector.

Selector Opcode Description
0 SAD Load DMA Address from word register
1 RAD Store DMA Address to word register
2 SCT Load DMA Count from word register
3 RCT Store DMA Count to word register
4 SDV Set DMA mode. Mode is constant in register nibble
5 RDV Set DMA mode. Mode is read from register in register nibble. Will always use the low byte even if a high byte register is provided
6 EAB Enable DMA
7 DAB Disable DMA
8 SMN Load low three bits of Internal Status Register from register. Will always use the low byte even if a high byte register is provided
9 RMN Store Internal Status Register to register. This instruction is buggy and will only store some of the bits depending on the register provided (the status register is masked on the inverse of the register number). Best results will be with AH. Will always use the low byte even if a high byte register is provided