OpC_10 1F - Nakazoto/CenturionComputer GitHub Wiki
OpCodes 0x10 ~ 0x1F
Quick Jump Table
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0x10: BL
Branch if Link/carry set (CPU5/CPU6)
The Link flag is roughly equivalent to a carry flag in other CPU architectures. This instruction will branch to a specified address if the Link flag is set. The Link flag can be set or reset by any of the following conditions or operations:
- The Link flag is reset by RL, set by SL, and complemented by CL.
- The Link flag is reset by all clear instructions.
- The Link flag is set or reset by the shift and rotate instructions.
- The Link flag is cleared and set if an arithmetic (except increment and decrement) instruction carries out.
Example:
* Default MUX interrupt handler to just reset the interrupts on the MUX cards.
MUXLVL EQU 6 ; Interrupt level of the MUX interrupt.
MAXCRTS EQU 2*4 ; Number of possible CRTs (2 cards x 4 ports).
MUXBUFF DB 0,MAXCRTS ; Buffer to hold the last byte received.
RIMUX RI ; Return from interrupt.
MUXINT CLA ; A = 0.
LDX= MUX0 ; X = address of first MUX.
XFR= MUXBUFF,Y ; Y = address of MUX buffer.
LDAB/ X'F20F' ; Get MUX interrupt info (clears the interrupt).
SRAB ; AL >> 1.
BL RIMUX ; If transmit interrupt, return.
LDB= B'11' ; B = CRT# mask.
NABB ; BL = AL & BL. BL = CRT#.
ADD B,Y ; Y = B + Y.
SLRB BL ; BL = BL << 1. BL = offset of CRT#.
SRR A,3 ; A = A >> 3. A = MUX#.
SLR A,2 ; A = A << 2. A = offset in MUX buffer.
ADD A,Y ; Y = A + Y. Y = address of MUX buffer byte.
SLR A,2 ; A = A << 2. A = offset of MUX#.
ADD A,X ; X = address of interrupting MUX.
ADD B,X ; X = address of CRT on MUX.
LDAB+ X+ ; AL = status of CRT on MUX. X = data address.
LDAB+ X ; AL = data of CRT on MUX.
STAB+ Y ; Store data byte in buffer.
JMP RIMUX ; Jump to the return.
The above code is an interrupt handler for MUX cards within CNake. Notably, interrupt information is received via the MMIO address X'F20F' and stored in the A register. The A register is then shifted right, moving the bit we are interested in to the right, looping around into the Link register. If the Link register is set, we branch to RIMUX and return from the interrupt.
0x11: BNL
Branch if Link/carry Not set (CPU5/CPU6)
The Link flag is roughly equivalent to a carry flag in other CPU architectures. This instruction will branch to a specified address if the Link flag is not set. The Link flag can be set or reset by any of the following conditions or operations:
- The Link flag is reset by RL, set by SL, and complemented by CL.
- The Link flag is reset by all clear instructions.
- The Link flag is set or reset by the shift and rotate instructions.
- The Link flag is cleared and set if an arithmetic (except increment and decrement) instruction carries out.
Example:
MOVESNAKE STK X,2 ; Push X to the stack.
XFR= SNAKEDIR,Z ; Z = snake direction table.
LDA/ GAMESCORE ; A = game score = snake length.
SLA ; A = A << 1. A = offset of one past head row/col.
XAY ; A -> Y.
LDX= SNAKERC ; X = snake row/column table.
ADD Y,X ; X = one past snake head row/col pointer.
LDB- X- ; X = pointer to head row/col; B = head row/col.
SRR Y ; Y = Y >> 1. Y = offset of one past head dir.
ADD Y,Z ; Z = one past snake head direction pointer.
LDAB- Z- ; Z = pointer to head direction; AL = head dir.
SRAB ; A = A >> 1.
BNL MSRIGHT ; If not left, try right.
DCR B ; Subtract one from the column.
JMP MSFOOD ; Check if food is there.
The above code handles snake movement within CNake. Notably, the A register is loaded with the value in Z, which is a pointer indicating head direction. This value is then shifted one bit to the right, moving the bit we are interested in into the Link register. If the Link register is not set, then the direction is still unknown and we branch to MSRIGHT to enact the same test on a different direction.
0x12: BF
Branch if Fault set (CPU5/CPU6)
This instruction will branch to a specified address if the Fault flag is set. The Fault flag can be set or reset by any of the following conditions or operations:
- The Fault flag is reset by RF and set by SF.
- The Fault flag is reset by all clear instructions.
- The Fault flag is set or reset by the shift, rotate, and arithmetic instructions depending on the MSB changing.
Example:
BF LOCATION ; Branch to LOCATION if Fault flag is set.
Unfortunately, I have not found a good example of a BF operation within actual code. When we have a better example, I will update this page.
0x13: BNF
Branch if Fault Not set (CPU5/CPU6)
This instruction will branch to a specified address if the Fault flag is not set. The Fault flag can be set or reset by any of the following conditions or operations:
- The Fault flag is reset by RF and set by SF.
- The Fault flag is reset by all clear instructions.
- The Fault flag is set or reset by the shift, rotate, and arithmetic instructions depending on the MSB changing.
Example:
BNF LOCATION ; Branch to LOCATION if Fault flag is not set.
Unfortunately, I have not found a good example of a BNF operation within actual code. When we have a better example, I will update this page.
0x14: BZ
Branch if Zero
MORE EXPLANATION.
DELY DLY ; 4.55ms delay
DCR Y ; Decrement Y value
BNZ DELY ; Branch if Not Zero to DELY
RSR ; Return from Subroutine
This is short delay subroutine that counts down the Y value and loops back to the label DELY
until the Y value reaches 0, at which point it returns from the subroutine. On each iteration it runs a check to see if Y has reached 0. If Y is anything other than 0, the BNZ operation causes it to branch/jump up to the label DELY
. If Y is equal to 0, the BNZ operations allows the program to continue to the next instruction.
0x15: BNZ
Branch if Not Zero
MORE EXPLANATION.
Example:
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0x16: BM
Branch if Minus set
MORE EXPLANATION.
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0x17: BP
Branch on Positive
MORE EXPLANATION.
Example:
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0x18: BGZ
Branch if Greater than Zero
MORE EXPLANATION.
Example:
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0x19: BLE
Branch if Less than or Equal to zero
MORE EXPLANATION.
Example:
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0x1A: BS1
Branch is Sense switch 1 is set
MORE EXPLANATION.
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0x1B: BS2
Branch is Sense switch 2 is set
Example:
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0x1C: BS3
Branch is Sense switch 3 is set
MORE EXPLANATION.
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0x1D: BS4
Branch is Sense switch 4 is set
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0x1E: BI
TEXT
MORE EXPLANATION.
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0x1F: BCK
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