OpC_00 0F - Nakazoto/CenturionComputer GitHub Wiki
OpCodes 0x00 ~ 0x0F
0x00: HLT
Halts the CPU6
The HLT instruction will check the current interrupt level. If the interrupt level is 15, then the CPU6 enters the Halt state which can be exited with a backplane interrupt or DMA interrupt, or by toggling the R or I dip switches. If the interrupt level is not 15, then HLT will trigger an abort trap with value 1.
Example:
XFR= X'00FF',Z ; Load Z reg. with a value of FF
CLR X ; Clear X register to zero
TOP INR X ; Increment X reg. by one
XFR X,Y ; Transfer counter into Y
SUB Z,Y ; Subtracts Z-Y
BNZ TOP ; Branch if Not Zero to TOP
HLT ; If Zero, restart whole program
This is a simple loop that initially sets Z to a value of 0x00FF
and clears the X register to 0. It then copies X to Y and subtracts Y from. It then tests if the result is 0, and if it is not zero (ie. Z is not equal to Y), it jumps back to TOP
, increments X and tests again. If the result is zero, it skips to HLT
which will Halt the CPU. This illuminate the HALT LED on the front panel and the system must be restarted from there.
0x01: NOP
No operation
NOP does not have any microcode, the initial instruction decoding provides the microcode address for the start of the instruction loop.
Example:
NOP
0x02: SF
Set the fault flag
Other flags are unaffected. MORE EXPLANATION.
Example:
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0x03: RF
Reset the Fault flag to zero
Other flags are unaffected. MORE EXPLANATION.
Example:
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0x04: EI
Enable Interrupt
MORE EXPLANATION.
Example:
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0x05: DI
Disable Interrupt
MORE EXPLANATION.
Example:
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0x06: SL
Set Link/carry
MORE EXPLANATION.
Example:
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0x07: RL
Reset Link/carry
MORE EXPLANATION.
Example:
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0x08: CL
Complement/invert link/carry
MORE EXPLANATION.
Example:
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0x09: RSR
Return from SubRoutine
When a Jump SubRoutine instruction is run, the X register is pushed to the stack to save its current value, the PC is copied to X, and the effective address (EA) is then copied to the PC. When the program hits the Return from SubRoutine instruction, X is copied into the PC and then X is popped from the stack to restore it's original value.
There is a lot more going on behind the scenes, but from a programmer's perspective, this can be thought of as mostly standard subroutine control behavior.
Example:
CLR X,1 ; Clears X register and initializes with a 1
LOOP XFR X,Y ; Transfer X register into Y
JSR/ DELY ; Jump to DELY subroutine
INR X ; Increment X value
JMP LOOP ; Jump to LOOP label
DELY DLY ; 4.55ms delay
DCR Y ; Decrement Y value
BNZ DELY ; Branch if Not Zero to DELY
RSR ; Return from Subroutine
This is a short loop that initially sets the Y register to 0 and then loops forever. Each iteration the Y register increments, meaning the DELY
subroutine loops and delays for longer and longer each time. The RSR
instruction at the end tells the subroutine to return to the instruction after JSR
that sent it to the subroutine initially and to continue along.
0x0A: RI
Return from interrupt
MORE EXPLANATION.
Example:
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0x0B: Illegal Operation
Illegal instructions will trigger an abort trap. The instruction 0B has a different initial instruction decoding from the rest of the illegal instructions. On the EE200 this is an RIM instruction. It's possible that this instruction was never used by Centurion and was replaced by a user mode instruction on the CPU5. Possibly it was removed from the CPU6 as it was replaced by another instruction.
0x0C: SYN
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MORE EXPLANATION.
Example:
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0x0D: PCX
Transfer PC to X
Example:
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0x0E: DLY
4.55 ms delay
Example:
DELY DLY ; 4.55ms delay
DCR Y ; Decrement Y value
BNZ DELY ; Branch if Not Zero to DELY
RSR ; Return from Subroutine
This is short delay subroutine that counts down the Y value and loops back to the label DELY
until the Y value reaches 0, at which point it returns from the subroutine. Each time it loops back to the label, it executes the DLY
instruction, which cause the CPU to delay for 4.55ms. If the Y value is 0x0F, the subroutine will loop 16 times, resulting in a delay of 72.8ms.
0x0F: RSV
Return from SVC
Example:
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