Microcode - Nakazoto/CenturionComputer GitHub Wiki
Microcode
Additional Microcode information at this link.
The microcode is a 56 bit mainly horizontal microcode controlled by AM2909 and AM2911 sequencers. Vertical aspects of the microcode are:
- Constants and conditional selection/update masks are stored in the same field as the direct inputs to the sequencers;
- The B Register Select field is used as inputs to an addressable latch, and possibly another input;
- Control signals are encoded.
Microcode word format
Bit 55 is MSB.
| Bit | Board Rom | PL Pins | Function | Comments |
|---|---|---|---|---|
| 3-0 | E3 | D2/D3 Decoder Input | Decoded before loaded into pipeline register. | |
| 6-4 | E3 | E6 Decoder Input | ||
| 7 | E3 | K11 Decoder Input bit 0 | ||
| 9-8 | J3 | K11 Decoder Input bit 1-2 | ||
| 12-10 | J3 | H11 Decoder Input | ||
| 14-13 | J3 | E7 Decoder Input | Pin 3 on decoder grounded | |
| 15 | J3 | J5 pin 2 | K9 multiplexer enable | Used for conditional calculation |
| 23-16 | M3 | Low 8 bits of sequencer direct input, constant input to data bus (inverted) | D2/D3 address 13 enables constant. Also used for conditional select | |
| 26-24 | L3 | High 3 bits of sequencer direct input | ||
| 27 | L3 | Sequencer stack enable (!FE) | ||
| 28 | L3 | Sequencer push or pop (PUP) | ||
| 30-29 | L3 | Sequencer 0-3 mux select (inverted) | ||
| 31 | L3 | Sequencer 4-7 mux select S0 (inverted) | Confirm K6 pin 3 to L9 pin 10 | |
| 32 | H3 | H5 pin 19 | Sequencer 4-7 mux select S1/1 | Confirm J6 pin 5 from H5 pin 19. Combines with bit 54 |
| 33 | H3 | H5 pin 16 | Case control | Confirm J13/K13 enable pins from H5 pin 16 |
| 36-34 | H3 | AM2901 I210 inputs | ||
| 39-37 | H3 | AM2901 I543 inputs | Confirm AM2901 pins 26, 28, 27 respectively from H5 pins 15, 5 and 2 | |
| 42-40 | F3 | AM2901 I876 inputs | ||
| 46-43 | F3 | AM2901 B Register Select | Confirm from F5 pins 9, 12, 15 and 5 to AM2901 pins 17-20. Note also used as input to F11 'LS259 addressable latch for CPU control. Possibly also for M13 'LS259 | |
| 47 | F3 | AM2901 A Register Select bit 0 | A Register Select. | |
| 50-48 | K3 | AM2901 A Register Select bit 3-1 | Confirm K5 pins 19 and 6 to AM2901 pins 3 and 1 | |
| 51 | K3 | Shift/Carry input to AM2901 mux S0 | ||
| 52 | K3 | Shift/Carry input to AM2901 mux S1 | Confirm K5 pin 12 to F6 pin 2 | |
| 53 | K3 | K5 pin 15 | Hi/Low Register. | Controls whether high or low byte is read/written during register access |
| 54 | K3 | Sequencer 4-7 mux select S1/2 | Combines with bit 32 | |
| 55 | K3 | K5 pin 2 | Register at IPL | Determines whether Register index or IPL is used for register access |
Decoder enable lines
E7 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | Bus operation abort | nor gate at E8 controlling E14 74LS74 pin 1 |
| 2 | Load FLR | enable on J9 74LS378 |
| 3 | Bus wait | nor gate at E8 |
| 4 | unused | pin 3 on E7 is grounded |
| 5 | unused | pin 3 on E7 is grounded |
| 6 | unused | pin 3 on E7 is grounded |
| 7 | unused | pin 3 on E7 is grounded |
H11 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | Bus Read | |
| 2 | Bus Write | |
| 3 | Load Work AR High | Enables load on the high word of the work AR 'LS669s |
| 4 | Increment/decrement Work AR | |
| 5 | Increment/decrement MAR | |
| 6 | PROM enable/ALU disable | |
| 7 | Load Nibble Swapper | C11 and C12 |
K11 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | ||
| 2 | M13 'LS259 enable | enables latching to start/stop CPU operations |
| 3 | F11 'LS259 enable | enables latching to start/stop CPU operations |
| 4 | Register write | Same decoding in basic gates with alternate clocking |
| 5 | Load Page File | Loads the Result Register into the page file |
| 6 | Load Work AR Low | Enables load on the low word of the work AR 'LS669s (consistent with microcode) |
| 7 | Load Data Register | Tx register on AM2907s |
E6 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | Load RR | Load data register used for updating lots of things ('LS377 at C9) |
| 2 | Load RIR | Load register index ('LS377 at C13) |
| 3 | Load CLR | Interrupt Level |
| 4 | Load MAP | Load PT MAP register. Used with address lines for PT entry address |
| 5 | Load MAR | Load Memory Address Register (outer 'LS669s) from work address register (inner 'LS669s) |
| 6 | Load Seq AR | Load the sequencer AR. Likely only on the AM2909s |
| 7 | Load CCR | Load CC based on CONST field in microcode |
D2 74S139 (half) and D3 74S138
Note that these addresses get decoded before storage in the pipeline register.
| Address | Function | Notes |
|---|---|---|
| 0 | Read Swapped | Enable on C11/12 'LS173 tristate ffs |
| 1 | Read Register | Read the contents of the ISA register from D14 'LS374 |
| 2 | Read Address High | Read high byte of bus address before page lookup (real PC). Note bits 12-15 inverted |
| 3 | Read Address Low | Read low byte of bus address |
| 4 | Unused | |
| 5 | Unused | |
| 6 | Unused | |
| 7 | Unused | |
| 8 | Read Page | Read the page address (top 7 bits of paged address + MMIO select) |
| 9 | Read CCR | Read sense switches (1-4) low nibble and condition codes high nibble |
| 10 | Read Data Bus | AM2907s |
| 11 | Read Current Level | Enable on 'LS368 tristate inverter H14 and T18-21 from backplane bus |
| 12 | Read Req Level | Read other dip switches switches low nibble and interrupt request level from backplane high nibble |
| 13 | Constant | Constant from microcode word (inverted) |
| 14 | Unused | |
| 15 | Unused |
F11 lines
| Address | B select | Function |
|---|---|---|
| 0 | 0, 1 | Interrupt enable (on = enabled). Controlled by EI/DI instructions |
| 1 | 2, 3 | Address Bus enable (off = enabled) |
| 2 | 4, 5 | DMA address increment control? |
| 3 | 6, 7 | Increment/Decrement control of address register Off is decrement |
| 4 | 8, 9 | DMA control? |
| 5 | 10, 11 | Controlled by 96/a6 instructions. Parity Odd/Even? |
| 6 | 12, 13 | Controlled by 76/86 instructions. Parity check enabled (on = enabled) |
| 7 | 14, 15 | DMA enable (on). Controlled by 2f x6/x7 instruction. x6 enables |
M13 lines
| Address | B select | Function |
|---|---|---|
| 0 | 0, 1 | DMA function, controlled by 2f x4/x5 instruction |
| 1 | 2, 3 | DMA function, controlled by 2f x4/x5 instruction |
| 2 | 4, 5 | Timer (RTC) enable |
| 3 | 6, 7 | |
| 4 | 8, 9 | Run/Halt front panel light |
| 5 | 10, 11 | Timer reset (off = reset) |
| 6 | 12, 13 | ABT front panel light |
| 7 | 14, 15 | Interrupt acknowledge |
Shift/Carry Multiplexers
| Shift/Carry | Carry | Left Shift | Right Shift |
|---|---|---|---|
| 0 | 0 | 0 | ALU sign (F3 on high nibble) |
| 1 | 1 | Flags Carry | Flags Carry |
| 2 | Flags Carry | ALU Sign | ALU Q0 |
| 3 | 0 | 1 | ALU Carry |
Condition Codes
Conditional branches, subroutine calls and condition code register setting is controlled by the microcode address/constant field.
Link/Carry
The condition code register Link/Carry bit is set from bits 8 to 6 in the microcode address field. Bit 5 disables the multiplexer and will force the link bit to be set to zero in the condition code register. This is an 8 to 1 multiplexer at J10 on the CPU6 board.
| Bits 8-6 (mux selector) | Set Link (Carry) flag from | Example usage |
|---|---|---|
| 0 | Link flag in condition code register | SF |
| 1 | Invert link flag in condition code register | CL |
| 2 | Link flag from last ALU flags store | INRB |
| 3 | Set | SL |
| 4 | From result register bit 4 | RI |
| 5 | RAM3 output on ALU | |
| 6 | RAM0 output on ALU | |
| 7 | Q0 output on ALU |
Fault/Overflow
The fault/overflow bit in the condition code register is set based on bits 4 and 3 in the microcode address field, and the fault field from the last ALU flags storage. Bit 2 disables the multiplexer and will force the fault bit to be set to zero in the condition code register. This is an 8 to 1 multiplexer at J11 on the CPU6 board.
| Bits 4-3 (mux selector) | ALU Flags Fault Field (mux selector) | Set Fault (overflow) flag from | Example usage |
|---|---|---|---|
| 0 | X | From result register (bit 5) | RI |
| 1 | X | Set | SF |
| 2 | X | Fault flag in condition code register | SC |
| 3 | 0 | 0 | |
| 3 | 1 | 1 |
Minus/Sign and Value/Zero
These flags are set from the same multiplexer, which is always enabled. The values are set based on bits 1 and 0 in the microcode address field. This is a dual 4 to 1 multiplexer at J12 on the CPU6 board.
| Bits 1-0 (mux selector) | Set Value (Zero) flag from | Set Minus (Sign) flag from | Example usage |
|---|---|---|---|
| 0 | Value flag in condition code register | Minus flag in condition code register | SF instruction |
| 1 | Flag Register zero | Flag register minus | INRB instruction |
| 2 | Result Register (bit 7) | Result Register (bit 6) | RI instruction |
| 3 | AND(Flag Register zero, Flag Register prev. zero) | Flag register minus | STX instruction |
Note: prev. zero is the previous value of the flag register zero. The zero flag output feeds back into the prev. zero on each flags register load.
Microcode conditional branches
The conditional branches in the microcode are controlled by two multiplexers which set the OR lines in the low nibble AM2909. The multiplexer selects are the from bits 8-5 of the microcode address field, and the enable is bit 33 of the microcode word. Usually only one OR line is significant on any conditional branch, other lines if active are masked out with the microcode address low nibble (e.g., if it is a conditional branch zero, there will be a mask of xx01 in the low nibble of the microcode address field). OR 0 and OR 1 are set by a dual 4 to 1 multiplexer at J13 on the CPU6 board. OR 2 and 3 are set by a dual 4 to 1 multiplexer at K13 on the CPU6 board.
Most of the conditional branches are one way (only one bit of the multiplexer output is relevant), but there are approximately five microcode locations where there is a multiway branch.
| Bits 8-5 (mux selectors) | OR 0 | OR 1 | OR 2 | OR 3 |
|---|---|---|---|---|
| 3 | 0 | 0 | Interrupts enabled | Link Condition Code |
| 7 | 0 | 0 | Halt? | Interrupt Request |
| b | 0 | 0 | DMA? | DMA? |
| c | Minus from flags | Zero from flags | 0 | 0 |
| d | Half carry from flags | Overflow from flags | 0 | 0 |
| e | Page table entry bit 8 zero | Valid Page | 0 | 0 |
Microcode conditional subroutine calls
Microcode conditional subroutine calls are controlled by a multiplexer which is selected from bits 2 to 0 of the microcode address field. This is also used to form part of the subroutine address. The conditional subroutine call is enabled by bit 15 of the microcode word. The conditions are selected by a multiplexer at K9 on the CPU6 board.
| Bits 2-0 (mux selector) | Branch on test | Example usage |
|---|---|---|
| 0 | Bus busy | |
| 1 | Bit 0 of RIR and Bit 4 of RIR both zero | |
| 2 | Bit 0 of RIR | BL instruction |
| 3 | Not memory read | |
| 4 | Not memory write | |
| 5 | DMA | |
| 6 | Parity Error | |
| 7 | Interrupt |
Significant Addresses
This is an incomplete list of significant addresses in the CPU6 microcode
| Address | Label | Function |
|---|---|---|
| 000 | Microcode start address | |
| 07e | Page Table Entry initialisation in bootstrap | |
| 100 | Instruction loop start. Some instructions restart the instruction loop at 101 | |
| 101 | Instruction loop start. Some instructions restart the instruction loop at 100. NOP entry | |
| 105 | CPU trap handler microcode? | |
| 107 | ?? BEP entry - is this still BEP? | |
| 119 | SF entry | |
| 14f | RF entry | |
| 156 | BGZ entry | |
| 17b | CL entry | |
| 17e | PCX entry | |
| 185 | SL entry | |
| 18b | Privileged instruction entry | |
| 18e | RIM entry (illegal instruction?) | |
| 193 | RSR entry | |
| 1af | RF entry | |
| 1b0 | 67 instruction entry | |
| 1ba | ?? BTM entry - is this still BTM? | |
| 1ca | ?? ELO entry - is this still ELO? | |
| 1ce | BS4 entry | |
| 1de | BS3 entry | |
| 1ee | BS2 entry | |
| 1f9 | BLE entry | |
| 1fa | BM/BP entry | |
| 1fb | BZ/BNZ entry | |
| 1fc | BF/BNF entry | |
| 1fd | BL/BNL entry | |
| 1fe | BS1 entry | |
| 48e | Save PC to register indexed by r09 in current IPL | |
| 76c | Test Q for zero, jump to caller/9 non-zero, caller/b zero. Caller pops stack |