MUX Board - Nakazoto/CenturionComputer GitHub Wiki

Multiplexer Boards

The Multiplexer (MUX) boards are the primary source of communication with the human. There was a lot of inconsistency in the data terminal world in the 70s and 80s as things were rapidly changing, so the MUX boards are capable of communicating in both RS-232 as well as Current Loop depending on the revision. The revision can be identified by the location of the crystal oscillator. Later revision boards had the crystal oscillator in the center of the board and these were capable of both RS-232 and current loop. Early revision boards, like the one pictured below, had the oscillator near Port 4 and were RS-232 only. The ADDS Regent 200 Terminal used with the Centurion system here is capable of both Current Loop and RS-232 and we do have an early revision board in the collection, but so far we have only tested with RS-232. Each MUX board contains four ports and multiple MUX boards can be used in parallel (at least/most 2?) to allow more users on to the system.

Port capabilities

  • Port 0, 1, and 2 are defaulted to 9600 baud, 7-bit ASCII, Even parity and 1 stop bit, or 9600-7-E-1.
  • Port 3 is defaulted to 300 baud for printers (unsure of the ASCII, parity and stop settings).
  • Each port is programmable via S.XSMCB to adjust the baud rate, ASCII, parity and stop bits.
    • Available baud rates: 75, 300, 1,200, 2,400, 4,800, 9,600, 19,200
    • Available ASCII data bits: 5, 6, 7, 8
    • Available parity options: Odd, Even, No Parity
    • Available stop bits: 1, 2
  • The MUX Control Byte Value can be set by following the operation below:

The desired control byte value to which UPSI is set is determined by the format which is to be used on the channel. The format is classified into four characteristics: data length, parity, number of stop bits transmitted, and baud rate. Several selections are available for each characteristic and each selection has a value associated with it. The control byte value is obtained by choosing one selection within each characteristic and adding up the values associated with the selections chosen.

The length characteristic defines the number of "data" bits per character, exclusive of start, parity, and stop bits. Four selections are available:

Number of Bits Control Byte Value
5 0
6 2
7 4
8 6

The parity characteristic defines whether a parity bit exists and if so, how it is computed. Three selections are available:

Parity Control Byte Value
Odd 0
Even 1
None 16

The number of stop bits transmitted characteristic defines the number of stop bits per transmitted character. It has no effect on received data. Two selections are available:

No. of Stop Bits Control Byte Value
1 0
2 8

ASCII CRT's and teletypes require one stop bit. Baudot devices require two.

The baud rate characteristic defines the rate at which data is transferred into and out of the channel. Eight selections are available:

Baud Rate (BPS) Control Byte Value
75 32
300 64
1,200 96
2,400 128
4,800 160
9,600 192
19,200 224

The 4-port interface must be modified if it 1is to operate at 19,200 baud.

The standard channel format is 7 bits, an even parity bit, and one stop bit, at 9,600 baud. This gives a control byte value of 4+1+0+192=197. If it were desired to set channel CRT2 to this format, it could be done with the following JCL statements:

.SETA UPSI=197
.USE CRTO FOR SYSO
.RUN [S.]XSMCB

MUX MMIO

There is enough MMIO space for 16 MUX cards. The second-lowest order nibble determines which MUX card the MMIO is selecting. All credit goes to Meisaka for the unbelievable work figuring all this out!

  • F20F -> Special interrupt information address
  • F2xF -> Reset
    • On Read = N/A
    • On Write = Clears interrupts, resets UARTs and most registers
  • F2xE -> Interrupt control
    • On Read = N/A
    • On Write = Interrupts on
  • F2xD -> Interrupt control
    • On Read = N/A
    • On Write = Interrupts off
  • F2xC -> Interrupt control
    • On Read = N/A
    • On Write = Software triggered transmit interrupt
  • F2xB -> Baud Rate control
    • On Read = N/A
    • On Write = Baud rate generator divisor (Baud = Crystal / (256 * (256 - N));N != 0
  • F2xA -> Interrupt control
    • On Read = N/A
    • On Write = Sets interrupt level
  • F2x9 -> Unused
    • On Read = N/A
    • On Write = N/A
  • F2x8 -> RTS Control
    • On Read = N/A
    • On Write = Allows setting which port uses RTS flow control
  • F2x7 -> MUX Port 3 Data I/O
    • On Read = Received Data
    • On Write = Transmit Data
  • F2x6 -> MUX Port 3 Status/Control
    • On Read = Read status of MUX port (Rx data available, Tx buffer empty, Parity error, Framing error, Overrun, Clear To Send)
    • On Write = Sets control of MUX port (Baud rate, Parity, Data length, Stop bit)
  • F2x5 -> MUX Port 2 Data I/O
    • On Read = Received Data
    • On Write = Transmit Data
  • F2x4 -> MUX Port 2 Status/Control
    • On Read = Read status of MUX port (Rx data available, Tx buffer empty, Parity error, Framing error, Overrun, Clear To Send)
    • On Write = Sets control of MUX port (Baud rate, Parity, Data length, Stop bit)
  • F2x3 -> MUX Port 1 Data I/O
    • On Read = Received Data
    • On Write = Transmit Data
  • F2x2 -> MUX Port 1 Status/Control
    • On Read = Read status of MUX port (Rx data available, Tx buffer empty, Parity error, Framing error, Overrun, Clear To Send)
    • On Write = Sets control of MUX port (Baud rate, Parity, Data length, Stop bit)
  • F2x1 -> MUX Port 0 Data I/O
    • On Read = Received Data
    • On Write = Transmit Data
  • F2x0 -> MUX Port 0 Status/Control
    • On Read = Read status of MUX port (Rx data available, Tx buffer empty, Parity error, Framing error, Overrun, Clear To Send)
    • On Write = Sets control of MUX port (Baud rate, Parity, Data length, Stop bit)

MUX Interrupt Order of Operations

Read:

MUX receives a byte

  • Byte received by MUX and stored in buffer
  • MUX performs interupt request
    • MUX checks if INT_IN = off AND CPL < 6
    • MUX hits Interrupt Request INTRQ
    • OS sends back Interrupt Acknowledge INT_ACK
    • MUX sets Interrupt Level INR{0~3} to lvl. 6
    • OS changes to CPL = 6
    • OS asserts MMIO 0xF20F read for info on what's going on
      • (Reading 0xF20F clears the interrupt condition [INTRQ,INR{0~3}])
  • OS asserts RDIN requesting byte (0xF2F1 for tape)
  • MUX asserts Address Pre-empt APRE
  • MUX asserts Data Bus with new byte
  • MUX asserts Data Ready DRDY
  • OS grabs byte off of data bus
  • MUX turns DRDY and APRE off when OS turns RDIN off

Write:

OS wants to send a byte

  • WTIN is asserted by OS requesting send op (0xF2F1)
  • MUX asserts Address Pre-empt APRE
  • MUX grabs byte on Data Bus copies it to buffer
  • MUX starts shifting buffer out
  • MUX asserts Data Ready DRDY
  • OS turns WTIN off
  • MUX turns Data Ready DRDY off

MUX finishes shifting byte out

  • MUX performs interupt request
    • MUX checks if INT_IN = off AND CPL < 6
    • MUX hits Interrupt Request INTRQ
    • OS sends back Interrupt Acknowledge INT_ACK
    • MUX sets Interrupt Level INR{0~3} to lvl. 6
    • OS changes to CPL = 6
    • OS asserts MMIO 0xF20F read for info on what's going on
      • (Reading 0xF20F clears the interrupt condition [INTRQ,INR{0~3}])

Schematic

Meisaka is doing incredible work to reverse engineer the MUX board. It's stunning what's been accomplished so far, without having the actual hardware at hand!

Meisaka's Github

Right click and "Save As..." or "Open Image in New Tab" to see full resolution of schematics. Visit their Github for the original files to the most up to date and highest resolution files.

Meisaka's Schematic: