CPU6 Internal Registers

The CPU6 contains a number of internal registers that are under microprogram control. Most of these registers are not user accessible.

Register name	Board designator(s)	Device(s)	Function	Input	Output	Load enable
pipeline	UM5, UL5, UK5, UJ5, UH5, UF5, UE5	'377, '174	Microword pipeline register(s)	Microprogram ROM		N/A
FLR	UJ9	'378	Flag register	ALU0, ALU1		E7.2 (LOAD.FLR)
MAR_LSB	UB1, UC1	'669	Bus address low byte	addr_work_lo	Address bus	TBD
MAR_MSB	UB6, UC6	'669	Bus address high byte	addr_work_hi	Address bus	TBD
WAR_LSB	UB2, UC2	'669	Work address low byte	Addr bus/F/DP?	addr_lo	K11.6
WAR_MSB	UB6, UC6	'669	Work address high byte	Addr bus/F/DP?	addr_hi	H11.3
RIR	UC13	'377	User register address	BUS.F	Reg. RAM addr	E6.2 (LOAD.RIR)
RR	UC9	'377	User register value	BUS.F	Reg. RAM value	E6.1 (LOAD.RR)
CCR	M12	'378	Condition codes			E6.7 (LOAD.CCR)
CPU State	Internal to ALU		Internal store of PTBR and CPU state bits