Instructions - Nakazoto/CenturionComputer GitHub Wiki
Instructions
This is a list of the available registers, OpCodes / Instructions, and what they mean. These were all reverse engineered by just looking at existing code and recognizing patterns. As such, this list may be incomplete or full of errors. Any resemblance to the mnemonics or syntax used by other processors, such as the 8086, is simply a coincidence as this ISA has its roots in the Eldorado Electrodata Corporation EE200 which hails from approximately 1971. Documentation on the EE200 can be found here. Most of this information is specifically for the CPU6, the CPU5 and CPU4 all have their own quirks that must be accounted for when writing assembly.
Note, the previous page that was here is outdated, but if you're still looking for something that was on that page, it is available here.
P.ASM
Everything here is designed to be able to allow you to write assembly that can be assembled using the built-in Centurion assembler. This assembler will also output direct Hexadecimal that can be copied when using the PRT0 option.
Registers
There are eight registers available, though care should be taken with some registers, particularly the X, S, C and P registers, as these are used for specific functions during some OpCodes. For more information, refer to this page on the Registers.
Suffixes and Building the OpCode
Suffixes are a major key to using Centurion assembly. Each assembly statement consists of:
- A Base mnemonic (eg.
LDAfor LoaD A register)- Refer to the OpCode List below for more information.
- A size suffix (eg.
LDABfor LoaD A register Byte)- No suffix means to perform the operation on the entire register. The suffix 'B' means to use the low-order byte of the register: AL, BL, XL, YL, ZL, SL, CL, PL. The high-order byte of the register (AU, BU, XU, YU, ZU, SU, CU, PU) is unaffected.
- An addressing mode (eg.
LDAB/for LoaD A register Byte with direct value)- Used for instructions that access memory. The suffixes and their usage can be quite complex. Refer to the following section for more information.
Addressing Modes
Addressing modes are a type of suffix added to the base mnemonic+size suffix and used for instructions that access memory. The suffixes are as follows:
| Suffix | Usage | Notes |
|---|---|---|
| = | Literal | The byte or word argument to the instruction is used as the value. |
| / | Direct | The word argument to the instruction is used as the address in memory to get the value from. |
| $ | Indirect | The word argument to the instruction is used as the address of a word in memory which is used as the address to get the value from. |
| Relative | (This a space character, not a blank) The argument to the instruction is taken as a displacement from PC, or if it is a label, the displacement is calculated. The displacement must be in the range [-128,127] and is relative to the start of the next instruction. The displaced address is used as the address in memory to get the value from. | |
| * | Relative Indirect | The argument to the instruction is taken as a displacement from PC, or if it is a label, the displacement is calculated. The displacement must be in the range [-128,127] and is relative to the start of the next instruction. The displaced address is used as the address of a word in memory which is used as the address to get the value from. |
| + | Indexed Addressing | See below. |
| - | Indexed Addressing | See below. |
Indexed Addressing
Either '+' or '-' suffix works. There are 12 sub-modes of this mode, controlled by suffixing the argument to the instruction:
- ' ': use the register as an address.
- '+': use the register as an address, then increment the register by 1 (if 'B' suffix on the mnemonic) or 2 (if no 'B' suffix).
- '-': decrement the register by 1 (if 'B' suffix on the mnemonic) or 2 (if no 'B' suffix), then use the register as an address.
- ',nnn': use the register plus the displacement nnn as an address.
- '+,nnn': use the register plus the displacement nnn as an address, then increment the register by 1 (if 'B' suffix on the mnemonic) or 2 (if no 'B' suffix).
- '-,nnn': decrement the register by 1 (if 'B' suffix on the mnemonic) or 2 (if no 'B' suffix), then use the register plus the displacement nnn as an address.
- '*': use the register as an address of a word in memory to use as the address. Can be combined with any of the 6 suffix patterns above to form the other six sub-modes.
- The indexed addressing suffixes are also used for implicit indexing, which is just a shorter way to encode some operations that don't require post-increment or pre-decrement. When the low nibble of a memory opcode is 8-F, it is implicit indexing and allows for a single-byte encoding instead of a two-byte encoding to accomplish the same thing.
BIGNUM and MemBlock
There are of course exceptions to the addressing modes shown above, notably the BIGNUM and MemBlock instructions. Refer to each individual Operation in the full list below for more information.
OpCode List
This is a list of all the OpCodes and the mnemonic they use in P.ASM. However, their actual usage is far more complex. Scroll further down more detailed explanations on each code.
| Hex | Code | Hex | Code | _ | Hex | Code | _ | Hex | Code | |
|---|---|---|---|---|---|---|---|---|---|---|
| 00 | HLT | 01 | NOP | 02 | SF | 03 | RF | |||
| 04 | EI | 05 | DI | 06 | SL | 07 | RL | |||
| 08 | CL | 09 | RSR | 0A | RI | 0B | Illegal | |||
| 0C | SYN | 0D | PCX | 0E | DLY | 0F | RSV | |||
| 10 | BL | 11 | BNL | 12 | BF | 13 | BNF | |||
| 14 | BZ | 15 | BNZ | 16 | BM | 17 | BP | |||
| 18 | BGZ | 19 | BLE | 1A | BS1 | 1B | BS2 | |||
| 1C | BS3 | 1D | BS4 | 1E | BI | 1F | BCK | |||
| 20 | INRB | 21 | DCRB | 22 | CLRB | 23 | IVRB | |||
| 24 | SRRB | 25 | SLRB | 26 | RRRB | 27 | RLRB | |||
| 28 | INAB | 29 | DCAB | 2A | CLAB | 2B | IVAB | |||
| 2C | SRAB | 2D | SLAB | 2E | PageTable | 2F | DMA | |||
| 30 | INR/INC | 31 | DCR/DEC | 32 | CLR/CAD | 33 | IVR/IAD | |||
| 34 | SRR/SHR | 35 | SLR/SHL | 36 | RRR/RTR | 37 | RLR/RTL | |||
| 38 | INA | 39 | DCA | 3A | CLA | 3B | IVA | |||
| 3C | SRA | 3D | SLA | 3E | INX | 3F | DCX | |||
| 40 | ADDB | 41 | SUBB | 42 | ANDB | 43 | ORIB | |||
| 44 | OREB | 45 | XFRB | 46 | BIGNUM | 47 | MemBlock | |||
| 48 | AABB | 49 | SABB | 4A | NABB | 4B | XAXB | |||
| 4C | XAYB | 4D | XABB | 4E | XAZB | 4F | XASB | |||
| 50 | ADD | 51 | SUB | 52 | AND | 53 | ORI | |||
| 54 | ORE | 55 | XFR | 56 | EAO | 57 | DAO | |||
| 58 | AAB | 59 | SAB | 5A | NAB | 5B | XAX | |||
| 5C | XAY | 5D | XAB | 5E | XAZ | 5F | XAS | |||
| 60 | LDX= | 61 | LDX/ | 62 | LDX$ | 63 | LDX | |||
| 64 | LDX* | 65 | LDX+/- | 66 | SVC | 67 | MemBlock | |||
| 68 | STX+ A | 69 | STX+ B | 6A | STX+ X | 6B | STX+ Y | |||
| 6C | STX+ Z | 6D | STX+ S | 6E | LST | 6F | SST | |||
| 70 | Illegal | 71 | JMP/ | 72 | JMP$ | 73 | JMP | |||
| 74 | JMP* | 75 | JMP+/- | 76 | EPE | 77 | MUL | |||
| 78 | DIV | 79 | JSR/ | 7A | JSR$ | 7B | JSR | |||
| 7C | JSR* | 7D | JSR+/- | 7E | STK | 7F | POP | |||
| 80 | LDAB= | 81 | LDAB/ | 82 | LDAB$ | 83 | LDAB | |||
| 84 | LDAB* | 85 | LDAB+/- | 86 | DPE | 87 | Illegal | |||
| 88 | LDAB+ A | 89 | LDAB+ B | 8A | LDAB+ X | 8B | LDAB+ Y | |||
| 8C | LDAB+ Z | 8D | LDAB+ S | 8E | LDAB+ C | 8F | LDAB+ P | |||
| 90 | LDA= | 91 | LDA/ | 92 | LDA$ | 93 | LDA | |||
| 94 | LDA* | 95 | LDA+/- | 96 | SOP | 97 | Illegal | |||
| 98 | LDA+ A | 99 | LDA+ B | 9A | LDA+ X | 9B | LDA+ Y | |||
| 9C | LDA+ Z | 9D | LDA+ S | 9E | LDA+ C | 9F | LDA+ P | |||
| A0 | STAB= | A1 | STAB/ | A2 | STAB$ | A3 | STAB | |||
| A4 | STAB* | A5 | STAB+/- | A6 | SEP | A7 | Illegal | |||
| A8 | STAB+ A | A9 | STAB+ B | AA | STAB+ X | AB | STAB+ Y | |||
| AC | STAB+ Z | AD | STAB+ S | AE | STAB+ C | AF | STAB+ P | |||
| B0 | STA= | B1 | STA/ | B2 | STA$ | B3 | STA | |||
| B4 | STA* | B5 | STA+/- | B6 | ECK | B7 | Illegal | |||
| B8 | STA+ A | B9 | STA+ B | BA | STA+ X | BB | STA+ Y | |||
| BC | STA+ Z | BD | STA+ S | BE | STA+ C | BF | STA+ P | |||
| C0 | LDBB= | C1 | LDBB/ | C2 | LDBB$ | C3 | LDBB | |||
| C4 | LDBB* | C5 | LDBB+/- | C6 | DCK | C7 | Illegal | |||
| C8 | LDBB+ A | C9 | LDBB+ B | CA | LDBB+ X | CB | LDBB+ Y | |||
| CC | LDBB+ Z | CD | LDBB+ S | CE | LDBB+ C | CF | LDBB+ P | |||
| D0 | LDB= | D1 | LDB/ | D2 | LDB$ | D3 | LDB | |||
| D4 | LDB* | D5 | LDB+/- | D6 | STR | D7 | SAR | |||
| D8 | LDB+ A | D9 | LDB+ B | DA | LDB+ X | DB | LDB+ Y | |||
| DC | LDB+ Z | DD | LDB+ S | DE | LDB+ C | DF | LDB+ P | |||
| E0 | STBB= | E1 | STBB/ | E2 | STBB$ | E3 | STBB | |||
| E4 | STBB* | E5 | STBB+/- | E6 | LAR | E7 | Illegal | |||
| E8 | STBB+ A | E9 | STBB+ B | EA | STBB+ X | EB | STBB+ Y | |||
| EC | STBB+ Z | ED | STBB+ S | EE | STBB+ C | EF | STBB+ P | |||
| F0 | STB= | F1 | STB/ | F2 | STB$ | F3 | STB | |||
| F4 | STB* | F5 | STB+/- | F6 | LIO/SIO | F7 | MVL | |||
| F8 | STB+ A | F9 | STB+ B | FA | STB+ X | FB | STB+ Y | |||
| FC | STB+ Z | FD | STB+ S | FE | STB+ C | FF | STB+ P |
OpCode Breakdown
This is a breakdown of each OpCode, how it can be used and the appropriate syntax to use to ensure the assembly is compatible with P.ASM. The list is broken up into individual pages for collections of 16 OpCodes. Click the links for the OpCode you're looking for to find more information and examples of use.
0x00 ~ 0x0F
HLT, NOP, SF, RF, EI, DI, SL, RL, CL, RSR, RI, SYN, PCX, DLY, RSV
HLT = Halt
NOP = No operation
SF = Set fault
RF = Reset fault
EI = Enable interrupt
DI = Disable interrupt
SL = Set link/carry
RL = Reset link/carry
CL = Complement/invert link/carry
RSR = Return from subroutine
RI = Return from interrupt
SYN =
PCX = Transfer PC to X
DLY = 4.55 ms delay
RSV = Return from SVC
0x10 ~ 0x1F
BL, BNL, BF, BNF, BZ, BNZ, BM, BP, BGZ, BLE, BS1, BS2, BS3, BS4, BI, BCK
BL = Branch if link/carry set
BNL = Branch if link/carry not set
BF = Branch if fault set
BNF = Branch if fault not set
BZ = Branch if zero
BNZ = Branch if not zero
BM = Branch if minus set
BP = Branch on positive
BGZ = Branch if greater than zero
BLE = Branch if less than or equal to zero
BS1 = Branch if sense switch 1 is set
BS2 = Branch if sense switch 2 is set
BS3 = Branch if sense switch 3 is set
BS4 = Branch if sense switch 4 is set
BI = Branch if interrupts enabled
BCK = Branch if clock enabled
0x20 ~ 0x2F
INRB, DCRB, CLRB, IVRB, SRRB, SLRB, RRRB, RLRB, INAB, DCAB, CLAB, IVAB, SRAB, SLAB, PageTable, DMA
INRB = Increment byte
DCRB = Decrement byte
CLRB = Clear byte
IVRB = Invert byte
SRRB = Arithmetic shift byte right
SLRB = Arithmetic shift byte left
RRRB = Rotate byte right (wraps through carry)
RLRB= Rotate byte left (wraps through carry)
INAB = Increment A register byte
DCAB = Decrement A register byte
CLAB = Clear A register byte
IVAB = Invert A register byte
SRAB = Shift A register byte right
SLAB = Shift A register byte left
PageTable =
DMA =
0x30 ~ 0x3F
INR/INC = Increment word
DCR/DEC = Decrement word
CLR/CAD = Clear (or set) word
IVR/IAD = Invert word
SRR/SHR = Shift word register right
RRR/RTR = Rotate word register right
INA = Increment A register word
DCA = Decrement A register word
CLA = Clear A register word
IVA = Invert A register word
SRA = Shift A register word right
SLA = Shift A register word Left
INX = Increment X register word
DCX = Decrement X register word
0x40 ~ 0x4F
ADDB, SUBB, ANDB, ORIB, OREB, XFRB, BIGNUM, MemBlock, AABB, SABB, NABB, XAXB, XAYB, XABB, XAZB, XASB
ADDB = Add two byte registers
SUBB = Subtract two byte registers
ANDB = AND two byte registers
ORIB = OR two byte registers
OREB = XOR two byte registers
XFRB = Transfer byte register into byte register
BIGNUM = Variable-length integer operations
MemBlock = Memory block operations
AABB = Add A register low byte and B register low byte
SABB = Subtract A register low byte and B register low byte
NABB = AND A register low byte and B register low byte
XAXB = Transfer A register low byte into X register low byte
XAYB = Transfer A register low byte into Y register low byte
XABB = Transfer A register low byte into B register low byte
XAZB = Transfer A register low byte into Z register low byte
XASB = Transfer A register low byte into S register low byte
0x50 ~ 0x5F
ADD, SUB, AND, ORI, ORE, XFR, EAO, DAO, AAB, SAB, NAB, XAX, XAY, XAB, XAZ, XAS
ADD = Add two word registers
SUB = Subtract two word registers
AND = AND two word registers
ORI = OR two word registers
ORE = XOR two word registers
XFR = Transfer word register into word register
EAO = Enable abort on overflow
DAO = Disable abort on overflow
AAB = Add A register word and B register word
SAB = Subtract A register word and B register word
NAB = AND A register word and B register word
XAX = Transfer A register word into X register word
XAY = Transfer A register word into Y register word
XAB = Transfer A register word into B register word
XAZ = Transfer A register word into Z register word
XAS = Transfer A register word into S register word
0x60 ~ 0x6F
LDX = Load X register word
SVC = Service call
MemBlock = Memory block operations
STX = Store X register word
LST = Load status
SST = Store status
0x70 ~ 0x7F
JMP, EPE, MUL, DIV, JSR, STK, POP
JMP = Jump
EPE = Enable Parity Error
MUL = Multiply word register and word register
DIV = Divider word register and word register
JSR = Jump to subroutine
STK = Push to stack
POP = Pop from stack
0x80 ~ 0x8F
LDAB = Load A register byte
DPE = Disable Parity Error
0x90 ~ 0x9F
LDA = Load A register word
SOP = Set Odd Parity
0xA0 ~ 0xAF
STAB = Store A register byte
SEP = Set Even Parity
0xB0 ~ 0xBF
STA = Store A register word
ECK = Enable Clock
0xC0 ~ 0xCF
LDBB = Load B register byte
DCK = Disable Clock
0xD0 ~ 0xDF
LDB = Load B register word
STR = Store register
SAR = Store A register
0xE0 ~ 0xEF
STBB = Store B register byte
LAR = Load A register
0xF0 ~ 0xFF
STB = Store B register word
LIO/SIO = Load IO/Store IO
MVL = Move long