FFC Board

FFC stands for "Finch Floppy Controller," which means that this board is a controller board for both the CDC Finch Drive as well as a CDC Floppy drive. The FFC hardware supports one Floppy drive and up to three Finch drives, although there appears to be a bug in the FFC firmware/microcode which would cause a Floppy drive to conflict with a third Finch drive potentially leading to data loss.

The FFC card is actually composed of two cards connected through five connectors oriented between the boards. The connectors are actually just IC sockets soldered into place, and then there are five screws (four at the corners, one offset from center) that hold both boards firmly together. Only one board has the card edge connector. Even though the board only occupies one slot and one connector on the backplane, it is wide enough that no other cards can be placed in the next slot. This construction was done because this board uses the same AM2901 bit-slice architecture as the CPU6 and CMD boards, however it does not utilize the multiwire construction technique. Using just standard two-layer boards would not allow the same density possible as multiwire, which resulted in the ICs having to be split across two boards.

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FFC Board Architecture

The architecture of the FFC board is very similar to the CPU6 and CMD boards, utilizing an AM2901 based microcoded architecture, with the microcode stored in a series of ROM chips.

Front Side Board

The front board interfaces with the CPU backplane bus and provides the board microcontroller (AM2901 ALUs, Signetics 8X02 sequencer, 1024 x 64 bits of microcode ROM and associated control logic), the DMA interface and 4096 bytes of SRAM. The RAM is used for the drive control command buffer, the Finch drive read/write buffer and some internal registers.

CPU Interface

The FFC interface address is set by a small PROM which can be swapped to allow multiple FFC cards to be used in a Centurion system. The FFC card we have is configured to an address of F800. There are two directly accessible registers, the Command/Data register at address F800 and the Status register at address F801. The Command/Data register is bi-directional, the Status register is read only. Writing to the Status register will reset the FFC card. The register designations have been determined by reverse engineering the FFC and probably don't match the Centurion documentation.

The Status register is a four bit register used to inform the CPU of the current status of the FFC. The status register appears to have been consistently implemented across the Centurion disk IO cards.

Bit	Meaning
0 (lsb)	Data in Command/Data register waiting to be read by CPU. The FFC sets this bit when data is available in the Command/Data register to be read by the CPU and resets this bit once it has been read. Includes data provided by the FFC during DMA. The Centurion drive control code we have reverse engineered names this bit FOUT
1	Data in Command/Data register waiting to be read by FFC. The FFC sets this bit on a write to the Command/Data register from the CPU to the FFC and resets it when a new byte to the Command/Data register can be written by the CPU. Includes data provided by the CPU during DMA. The Centurion drive control code we have reverse engineered names this bit FIN
2	This bit is unused by the FFC and is always 0
3 (msb)	The FFC card is busy processing an instruction. FIN and FOUT can and will change while the FFC is busy. The Centurion drive control code we have reverse engineered names this bit BUSY. We think that the CPU should not attempt to directly read or write data to the Command/Data register while this bit is active unless it is required for the completion of a previous command.

The Command/Data register is used to provide instruction to the microcontroller, and is also used as the bus interface during DMA operations. Several commands require additional bytes to be provided through the register. Any errors from the FFC operation are also returned in the Command/Data register. A value of zero (0) indicates that there was no error.

The valid commands are documented in the table below.

Command Byte (Hex)	Meaning	Additional Bytes required	Additional Notes
1x	Read FFC RAM from address in low nibble	none	Only addresses 0-fh supported. RAM byte provided in Command/Data register
41	Set CRC seed	Two bytes for CRC seed	Possibly used for copy protection schemes or similar
43	DMA command into command buffer	none (command string provided through DMA)	Command buffer is from 11h to c2h in the FFC RAM
45	Execute command in command buffer	none
46	DMA CPU to FFC	Two bytes for FFC RAM address; two bytes for length	MSB in first additional byte for both address and length
47	DMA FFC to CPU	Two bytes for FFC RAM address; two bytes for length	MSB in first additional byte for both address and length
50	Read Drive Status Register 1	none	DSR1 byte provided in Command/Data register
51	Read Drive Status Register 3	none	DSR3 byte provided in Command/Data register
52	Read Drive Ready Status	none	Drive Ready status provided in Command/Data register. Low nibble is used for units 0 to 3
53	Read Floppy Clock Register	none	Floppy Clock Register provided in Command/Data register (Shift Register 1)
54	Read Floppy Data Register	none	Floppy Data Register provided in Command/Data register (Shift Register 2)
55	Read Floppy Double Sided	none	Command/Data register is negative (msb set) if floppy drive is double sided
56 - 5f	Unsupported	none	These command bytes won't directly error, but will have unsupported effects which could damage data
60	Load Drive Control Register 1	Byte to load
61 - 6f	Load Drive Control Register 2	Byte to load

Any other value provided as a command byte will result in an "INVALID COMMAND/FUNCTION" error.

FFC Commands

The usual way of controlling the drives is by providing a command string to the FFC and executing it. The Finch and Floppy drives have slightly different command string structures and completely different drive access commands. The command buffer length is 178 bytes long.

Floppy Drive Commands

Floppy drive commands start with a unit select followed by a track select. RTZ is a valid track select of track zero. The Floppy Unit Select is $2^0$ or 1. Following the track select, there are options for Format, Verify, Read and Write. Operations on the Floppy drives which read or write data use DMA directly for the read or write of the byte from the drive. The speed of the drive is slow enough that the data is not required to be buffered on the FFC.

Command (Hex)	Additional Bytes	Description
81	1	Unit Select. Must be first in the command string
82	0	RTZ. Must be second in the command string
83	1	Track. Must be second in the command string. For double sided drives, tracks 4eh to 99h are used for side 2
88	4	Read Sector. The Sector data is provided through DMA to the CPU. Additional bytes are Sector number, key length (unknown meaning currently), sector size. Command byte and additional bytes are repeated for multi-sector access
8e	4	Verify Sector. The Sector is compared with data provided through DMA from the CPU. Additional bytes are Sector number, key length (unknown meaning currently), sector size. Command byte and additional bytes are repeated for multi-sector access
8f	4	Format Track/First Sector. Must be third in command string. The sector is formatted with the data provided from the CPU via DMA. Additional bytes are Sector number, key length (unknown meaning currently), sector size. Additional sectors are formatted with the 92 command byte
91	4	Write Sector. The sector is formatted with the data provided from the CPU via DMA. Additional bytes are Sector number, key length (unknown meaning currently), sector size. Command byte and additional bytes are repeated for multi-sector access
92	4	Format Sector. Can only follow an 8f command byte. The sector is formatted with the data provided from the CPU via DMA. Additional bytes are Sector number, key length (unknown meaning currently), sector size.

Complete list of command bytes for Floppy drive access still to be determined.

Finch Drive Commands

tbd

FFC Memory Map

The FFC has 4096 bytes of RAM available for variables/internal registers and buffers.

RAM address	Size (Bytes)	Description
000h	1	Floppy track number
001h	2	Finch 1 cylinder number
003h	2	Finch 2 cylinder number
005h	1	Unused. We believe this is due to a bug in the microcode and should be the location of the Finch 3 cylinder number
006h	2	Finch 3 cylinder number
007h	1	Unknown Purpose Floppy register. This overlaps with the Finch 3 cylinder number, so appears to be a bug in the microcode
008h	1	The last error recorded from the FFC operation
009h	1	Unknown
00ah	2	Sector size
00bh	1	IRQ level. This overlaps with the Sector size, so appears to be a bug in the microcode and is evidence that Bus Interrupts weren't fully implemented
00ch	1	Command Buffer Index
00dh	1	Command Buffer Length
00eh	1	Command State (used to determine out of order command sequence - see Error Code 13h)
00fh	2	CRC seed (possibly used for copy protection schemes or similar)
011h	178 (b2h)	Command Buffer
0c3h	3901 (f3dh)	Finch read/write buffer

FFC Bus Interrupts

The FFC has circuitry to provide bus interrupts. However we believe that this was never fully implemented on the FFC card. There is no way of directly setting the IRQ level of the FFC card, and there appears to be a bug where the sector size location in the FFC RAM overlaps with the IRQ level. The FFC microcode will trigger an interrupt at the end of executing a command string if the IRQ level is greater than the current interrupt level. The steps required during interrupt handling to reset the FFC to a state where interrupts aren't repeatedly generated would be complex.

Because of the size of the board due to the twin board construction and circuitry on the board, the FFC would need to be located in the slot nearest the CPU to allow interrupts to function correctly. The information we have is that the FFC was often located away from the CPU, which would result in a gap between cards and would mean that interrupts from the FFC card would not function correctly.

This evidence suggests that the interrupt capability of the FFC card was never fully implemented.

Back Side Board

The back board contains the circuitry for controlling and reading/writing the drives and includes the drive interface connectors.

The functionality includes:

• Floppy drive clock synchronization;
• Timing for the microcontroller and read/write data;
• Drive status and control registers;
• MFM encoding and write pre-compensation for the floppy drive;
• CRC calculation and checking;
• Floppy Drive read and write shift registers;
• Finch Drive read and write shift registers;
• Finch Drive data verification;
• Finch Drive sector byte count.

Drive Status Register 1

The designation of Drive Status Register 1 is from the reverse engineering of the FFC card and probably doesn't match the Centurion documentation.

Bit	Meaning
0 (lsb)	Unit 0 (Floppy) selected
1	Unit 1 selected
2	Unit 2 selected
3	Unit 3 selected
4	Clock bit error (Floppy)
5	CRC error
6	Read enabled (Finch)
7 (msb)	Fault Reset enabled

Drive Status Register 2

The designation of Drive Status Register 2 is from the reverse engineering of the FFC card and probably doesn't match the Centurion documentation.

Bit	Meaning
0 (lsb)	The selected drive is ready
1	Drive Head Count bit 0 (lsb)
2	Drive Head Count bit 1
3	(Finch data signal)
4	Write Protect active
5	Write Fault active
6	Track/cylinder 0 active
7 (msb)	Index signal active

Drive Status Register 3

The designation of Drive Status Register 3 is from the reverse engineering of the FFC card and probably doesn't match the Centurion documentation.

Bit	Meaning
0 (lsb)	The step signal is active
1	The direction signal is active

Drive Control Register 1

The designation of Drive Control Register 1 is from the reverse engineering of the FFC card and probably doesn't match the Centurion documentation.

Bit	Meaning
0 (lsb)	Disable Floppy data input to shift registers
1	Enable check of Floppy MFM clock generator errors
2	Finch Read Enable
3	Fault Reset
4	Drive Select Unit 0
5	Drive Select Unit 1
6	Drive Select Unit 2
7 (msb)	Drive Select Unit 3

Drive Control Register 2

The designation of Drive Control Register 2 is from the reverse engineering of the FFC card and probably doesn't match the Centurion documentation.

Bit	Meaning
0 (lsb)	Step
1	Direction (Step direction)
2	Head Load (Floppy)/RTZ (Finch)
3	Finch/Floppy Head Select bit 0 (lsb)
4	Finch/Floppy Write Enable
5	Floppy low current (high track)/Finch Head Select bit 2 (msb)
6	Finch Head Select bit 1
7 (msb)	Floppy Write Data Enable (gate data from shift registers)

FFC Error Codes

If there is an illegal operation or unexpected result from the drives, the FFC will return an error code in the Command/Data register. These error codes are extracted from the FLEX and FINCH utilities from the Hawk drive SOFTERM platter.

Error Code	Drive	Text	Comments
11	Floppy/Finch	COMMAND STRING OVF
12	Floppy/Finch	INVALID COMMAND/FUNCTION
13	Floppy/Finch	COMMAND SEQ. ERROR
14	Floppy/Finch	COMMAND STRING OVERRUN
15	Floppy/Finch	INVALID MICRO-DEVICE
16	Floppy	INVALID BUSS ID	sic
17	Floppy/Finch	UNIT SELECT ERROR
18	Floppy/Finch	INVALID TRACK NUMBER
19	Finch	INVALID HEAD SELECT
1a	Finch	BUFFER ADDRESS ERROR
1b	Finch	DATA MARK ERROR
1c	Finch	ADDRESS MARK ERROR
1d	Finch	TIMEOUT ERROR
21	Floppy/Finch	RECORD NOT FOUND	FFC not synced to data on track
22	Floppy/Finch	KEY LENGTH ERROR	ID Key length on drive does not match request
23	Floppy/Finch	DMA LAG	Any DMA error detected by the FFC
24	Floppy/Finch	WRITE FAULT
31	Floppy/Finch	SEEK ERROR
32	Floppy/Finch	SEEK TO TRACK ZERO ERROR
33	Floppy/Finch	ON WRONG TRACK
34	Floppy/Finch	ADDRESS FORMAT ERROR
35	Floppy/Finch	ADDRESS CRC ERROR
36	Floppy/Finch	DATA PULSE MISSING
37	Floppy/Finch	MISSING CLOCK PULSE
38	Floppy/Finch	CLOCK BIT ERROR
39	Floppy/Finch	CLOCK GENERATOR ERROR
3a	Floppy/Finch	VERIFY ERROR
3b	Floppy/Finch	DATA CRC ERROR
3c	Floppy/Finch	TRACK ENDED WHILE WRITING
41	Floppy/Finch	DRIVE NOT READY
42	Floppy/Finch	DISC WRITE PROTECTED	sic
43	Floppy/Finch	LOAD COMMAND STRING ERROR
45	Floppy/Finch	EXECUTE COMMAND STRING ERROR

Schematic

Meisaka has once again done some staggeringly good reverse engineering work on the FFC cards. We believe the schematic is 99% done with only minor things left to verify. The quality of the PNG created for display here is lacking, so click this link here to view the full SVG file.

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ROM Backups

The FFC board contains 12 ROMs in total, 9 on the primary board, and 3 on the secondary board. There was a lot of water damage around the H6, H7 and H8 area on the board, and the ROMs were in rough shape. Getting clean reads was spotty at best, but I believe that the data shown here is all correct.

Board	Location	Usage	IC	Link
FFC	H1	Microcode	82S181	Link
FFC	H2	Microcode	82S181	Link
FFC	H3	Microcode	82S181	Link
FFC	H4	Microcode	TBP28S86AN	Link
FFC	H5	Microcode	82S181	Link
FFC	H6	Microcode	82S181	Link
FFC	H7	Microcode	82S181	Link
FFC	H8	Microcode	82S181	Link
FFC	A3	Microcode/Logic?	TBP18S030	Link
FFC	A4	Microcode/Logic?	TBP28L22	Link
FFC	B3	Microcode/Logic?	TBP18S030	Link
FFC	J7	Microcode/Logic?	TBP18S030	Link