CPU6 Micro-architecture

The Centurion CPU6 is a microcoded architecture. It uses two Am2909s and one Am2911 microcode sequencers to form an 11-bit microcode address. That address drives seven 2kB EPROMs to produce a 56-bit microword. The microword drives the inputs of a pipeline register. The pipeline register produces register/bus enables, Am2901 ALUs control signals, sequencer multiplexer signals, sequencer next address, and an 8-bit constant.

Below is a diagram of the CPU6 data path with enable signals. The enable signals are all generated from the microsequencer pipeline register under microprogram control.

Internal Registers

The Centurion computer has a specific set of registers it can use and multiple interrupt levels, but within the CPU6 itself, this is all handled in a very different way. As a result, it has it's own specific internal registers that are not user accessible.

Click here for more information on the internal register

Microcode

Again, the Centurion computer has a specific instruction set that the user can program, however, internal to the CPU6 card, things are very different. It has very different registers, dedicated busses, RAM, and all manner of wild stuff going on. And all of this wild stuff is controlled directly through microcode stored in ROMs on the CPU6 board itself.

Click here for more information on the microcode