CPU6 Board - Nakazoto/CenturionComputer GitHub Wiki

CPU6 Board

The CPU4 was the initial CPU design and was named the "CPU4" due to the fact that it was comprised of four separate cards: three CPU cards and one DMA card. The CPU5 integrated all of this into just two cards that were linked through connectors and filled up two slots. The CPU6 took the CPU5 design one step further and integrated it all onto a single board, using a complex multiwire design. The CPU6 uses the AM2900 series of chips along with microcode stored in a collection of ROMs to effectively emulate the original CPU4 TTL architecture. See the ROM Backups page or scroll to the bottom for copies of the ROM data. The overall construction and design is very, very similar to the CMD Board.

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Multiwire Construction

Multiwire construction is essentially an early method of achieving essentially an 8 layer board. The Multiwire board starts with an already complex 4-layer board, featuring a ground and power plane, then an upper and lower copper plane, and then adds an additional four layers of enameled wire held in place by epoxy. This enables an incredible amount of chip density to be achieved, which is how the two-board CPU5 was miniaturized to just a single board.

This did however come with some drawbacks. The Multiwire boards are incredibly fragile. Any flexing can cause the internal enameled wire to snap, essentially severing a trace. Not only does this cause failures or erratic behavior, the fault is incredibly difficult to trace down and troubleshoot, especially so without a full-fledged schematic for the CPU6.

Instruction List

A nearly full instruction list has been created based on some documentation that was found for the Eldorado Electrodata Corporation EE200 CPU, which we believe was a predecessor of the Centurion CPU4. The CPU5 and CPU6 do feature some differences, and we're not 100% certain what those differences are exactly yet, but as the machine becomes more and more usable, we are hopeful that we can nail down a complete instruction set.

Instructions are constructed a nibble at a time, like a Build a Bear. The high nibble of the high byte determines what kind of operation is being executed. It should be noted that the lowest bit of the high nibble determines whether we are doing a byte operation or a word operation (excluding Control, Branch, X register and Jump operations).

Instructions can be either 1-byte, 2-byte or 3-byte depending on the type of instruction. The second or third byte (if present) are related to addressing, or directing the instruction as to which location in memory to act upon. Addressing can be either implicit or explicit. Implicit means that no addressing is specified, and that specific instruction operates on only one specific location. Explicit means the programmer must state which location they will perform the operation on.

Click here for more information on CPU6 Instructions

For example, this is the WriteString subroutine from the DIAG board that we used when printing "Hellorld!"

Hex OpCode Address Note
81 f2 00 LDAL (0xf200) Load direct address 0xf200 into byte of AL register
2c SRAL Shift byte of implicit register AL left
2c SRAL Shift byte of implicit register AL left
11 f9 BNL (PC-0x06) Branch if link not set to 6 bytes behind program counter
85 41 LDAL XW, 1 Use register XW as address and load into AL, then increment XW after
15 01 BNZ (PC+0x01) Branch if not equal to zero to 0x01 bytes ahead current PC
09 RSR Return from subroutine
a1 f2 01 STAL (0xf201) Store byte of AL register directly into address 0xf201
73 ef JMP (PC-0x11) Jump to 11 bytes behind current PC

Basic Layout and Micro-architecture

The Centurion CPU6 is a microcoded architecture. It uses two Am2909s and one Am2911 microcode sequencers to form an 11-bit microcode address. That address drives seven 2kB EPROMs to produce a 56-bit microword. The microword drives the inputs of a pipeline register. The pipeline register produces register/bus enables, Am2901 ALUs control signals, sequencer multiplexer signals, sequencer next address, and an 8-bit constant.

Click here for more information on the Micro-architecture.

Below are two diagrams of the CPU6 data path with enable signals. The enable signals are all generated from the microsequencer pipeline register under microprogram control. This diagram was reverse engineered through truly mind-boggling work by Opposing_Solo and Meisaka.

And here are the functional blocks of the CPU6 overlaid onto the actual CPU6 board. Parts of functionality physically separated on the CPU6 board have common coloring. This diagram was reverse engineered by Sjsoftware.

Schematic

Sjsoftware and Meisaka are doing incredible work to reverse engineer the CPU6. At this current point, I believe the CPU6 has been completely reverse engineered and below are full and complete schematics! Their work has been absolutely mind-blowing, and it's stunning what they've been capable of.

Sjsoftware's Github

Meisaka's Github

Right click and "Save As..." or "Open Image in New Tab" to see full resolution of schematics. Visit their Github for the original files to the most up to date and highest resolution files.

Sjsoftware's Schematic:

Meisaka's Schematic:

ROM Backups

The CPU6 contains 8 ROMs in total that are all part of the microcode used to emulate the CPU4 Architecture.

Board Location Usage IC Link
CPU6 E3 Microcode AM27S191 Link
CPU6 F3 Microcode AM27S191 Link
CPU6 H3 Microcode AM27S191 Link
CPU6 J3 Microcode AM27S191 Link
CPU6 K3 Microcode AM27S191 Link
CPU6 L3 Microcode AM27S191 Link
CPU6 M3 Microcode AM27S191 Link
CPU6 B13 Combinatorial Logic for instruction decoding 6309 Link