CPU5 Board

The CPU4 was the initial CPU design and was named the "CPU4" due to the fact that it was comprised of four separate cards: three CPU cards and one DMA card. The CPU5 integrated all of this into just two cards that were linked through connectors and filled up two slots, much like the FFC Board. The CPU6 took the CPU5 design one step further and integrated it all onto a single board, using a complex multiwire design and a more fleshed out instruction set. The CPU5 shown here is an early revision with lots of bodge wires to fix design errors.

There are also two daughter boards attached to the PCBs. One contains two AMD source SRAM chips and the other jumper configurations. Initially Centurion was planning on using TI sourced SRAM chips, but TI discontinued the chip after Centurion had ordered its first batch of CPU5 cards from the PCB manufacturer. The AMD SRAM daughter board was the fix for these early boards.

Right click and "Save As..." or "Open Image in New Tab" for full resolution.

Instruction List

A nearly full instruction list has been created based on some documentation that was found for the Eldorado Electrodata Corporation EE200 CPU, which we believe was a predecessor of the Centurion CPU4. The CPU5 features some differences, and we're not 100% certain what those differences are exactly yet. The primary difference is that the CPU5 implemented better DMA features than the CPU4, but the ISA should be largely the same.

Instructions are constructed a nibble at a time, like a Build a Bear. The high nibble of the high byte determines what kind of operation is being executed. It should be noted that the lowest bit of the high nibble determines whether we are doing a byte operation or a word operation (excluding Control, Branch, X register and Jump operations).

Instructions can be either 1-byte, 2-byte or 3-byte depending on the type of instruction. The second or third byte (if present) are related to addressing, or directing the instruction as to which location in memory to act upon. Addressing can be either implicit or explicit. Implicit means that no addressing is specified, and that specific instruction operates on only one specific location. Explicit means the programmer must state which location they will perform the operation on.

Click here for more information on CPU6 Instructions

For example, this is the WriteString subroutine from the DIAG board that we used when printing "Hellorld!"

Hex	OpCode	Address	Note
81 f2 00	LDAL	(0xf200)	Load direct address 0xf200 into byte of AL register
2c	SRAL		Shift byte of implicit register AL left
2c	SRAL		Shift byte of implicit register AL left
11 f9	BNL	(PC-0x06)	Branch if link not set to 6 bytes behind program counter
85 41	LDAL	XW, 1	Use register XW as address and load into AL, then increment XW after
15 01	BNZ	(PC+0x01)	Branch if not equal to zero to 0x01 bytes ahead current PC
09	RSR		Return from subroutine
a1 f2 01	STAL	(0xf201)	Store byte of AL register directly into address 0xf201
73 ef	JMP	(PC-0x11)	Jump to 11 bytes behind current PC

Basic Layout and Micro-architecture

The moment, we are unsure of how the CPU5 differs from the CPU6 in terms of layout and architecture. As we go through reverse-engineering the CPU5 and microcode, we'll come back and update this page with our findings.

Schematic

At the moment, we have not started the reverse engineering process for the CPU5. Once we have a workable schematic, we'll come back and update this page with our findings.

ROM Backups

The CPU5 contains 7 ROMs in total that are all part of the microcode used to emulate the CPU4 Architecture. We have not backed up these ROMs yet, but that is top priority.