Backplane - Nakazoto/CenturionComputer GitHub Wiki

14-Slot Backplane

The backplane for the original CPU4 model was very simple, however for the CPU5 and CPU6 models, the backplane gained additional logic for the newly positioned bootstrap ROM as well as interfacing with the front panel. The backplane shown here is for a CPU6 system.

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Schematic

This schematic was reverse engineered by tracing out each individual line on the board itself. We are fairly confident it is mostly correct, but there could be errors still present.

It is important to note that the layout for the first slot is different than the rest. The first slot is reserved for the CPU6, the remaining slots are identical and the order of cards should not matter. However, there is a daisy chain interrupt pin that requires an unbroken string of cards to work appropriately (the pin is connected through the card and not through the backplane).

Additionally, a NE567 is used to create a phase shifted sine wave based on the mains frequency for an internal clock.

Connector Pinout

This is the connector pinout as best as we currently understand it.

7-Slot Backplane

The 7-slot backplane was used in desk systems and sized such that a more compact design could be achieved. This particular backplane is for a CPU5 system, and may therefore be a little different than a CPU6 backplane.

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PICTURES FORTHCOMING

Schematic

There is no schematic for the 7-slot backplane as yet.

4-Slot Backplane

The 4-slot backplane was used only for the Micro Plus systems, and usually contained a CPU6, 128k MEM, MUX, and FFC. This particular 4-slot backplane is out of the Micro Plus system on display at the Vintage Geek Museum in Tennessee.

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PICTURES FORTHCOMING

Schematic

There is no schematic for the 4-slot backplane as yet.

ROM Backups

The only ROM on the backplane is the TBP18S42 (or 6349) mask ROM that contains the bootstrap code for CPU5 and CPU6 systems.

Board Location Usage IC Link
BPN N/A Bootstrap TBP18S42 (6349) Link